From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 96468 invoked by alias); 8 Jun 2017 10:32:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 96457 invoked by uid 89); 8 Jun 2017 10:32:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f43.google.com Received: from mail-wm0-f43.google.com (HELO mail-wm0-f43.google.com) (74.125.82.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Jun 2017 10:32:08 +0000 Received: by mail-wm0-f43.google.com with SMTP id n195so28022796wmg.1 for ; Thu, 08 Jun 2017 03:32:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:cc:subject:references :date:in-reply-to:message-id:user-agent:mime-version; bh=4+inm5njOLykQd04Rj9vNKP9w5hZ8qLxKoV29t7mQmY=; b=I/2j0/6AE9Ntw72yzGgs1hdAcTqTZjHcWA7jkB4gRHk6Zlxrp8hTaz/QDHxSUN0OPc djOGVwmXOegJQ8DZ5dstyVzNJlMZzc+S4h8PSEyjW+/19CTGVZIZgnjmt0tEqr4eJbbO B3XEtgj0SDUodN+SFU9PBljTSoptKaSvvUMauV+qTID15p83VgOgAqyRSHPH5WR1P0QJ qBWmCwsm44j5jlvE5GnRcnxjBSPgelGoS6SgxHOknd1ft7LwlwFU/vYZG3AcMAs2wJqM lHBf4IV0PAImBPocDaayDeroFlChI9l15JV/6lrUfqBhLwpXAjMNEycLHS9k4eIdunwQ HUUg== X-Gm-Message-State: AKS2vOwRy+swA05Og3FwgOMCslIZX8TRx5Ma/rZentWGKrT9smnJPpad txDgc1E0WY/rymLe X-Received: by 10.28.21.7 with SMTP id 7mr2849865wmv.39.1496917930572; Thu, 08 Jun 2017 03:32:10 -0700 (PDT) Received: from localhost (92.40.248.150.threembb.co.uk. [92.40.248.150]) by smtp.gmail.com with ESMTPSA id y41sm4389237wrd.59.2017.06.08.03.32.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Jun 2017 03:32:09 -0700 (PDT) From: Richard Sandiford To: Tamar Christina Mail-Followup-To: Tamar Christina ,GCC Patches , nd , James Greenhalgh , "Marcus Shawcroft" , Richard Earnshaw , richard.sandiford@linaro.org Cc: GCC Patches , nd , James Greenhalgh , "Marcus Shawcroft" , Richard Earnshaw Subject: Re: [PATCH][GCC][AArch64] optimize float immediate moves (1 /4) - infrastructure. References: Date: Thu, 08 Jun 2017 10:32:00 -0000 In-Reply-To: (Tamar Christina's message of "Wed, 7 Jun 2017 11:38:30 +0000") Message-ID: <8760g6bwig.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2017-06/txt/msg00492.txt.bz2 Tamar Christina writes: > @@ -4613,6 +4615,66 @@ aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode mode) > return true; > } > > +/* Return the binary representation of floating point constant VALUE in INTVAL. > + If the value cannot be converted, return false without setting INTVAL. > + The conversion is done in the given MODE. */ > +bool > +aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *intval) > +{ > + machine_mode mode = GET_MODE (value); > + if (GET_CODE (value) != CONST_DOUBLE > + || !SCALAR_FLOAT_MODE_P (mode) > + || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) > + return false; > + > + unsigned HOST_WIDE_INT ival = 0; > + > + /* Only support up to DF mode. */ > + gcc_assert (GET_MODE_BITSIZE (mode) <= 64); > + int needed = GET_MODE_BITSIZE (mode) == 64 ? 2 : 1; > + > + long res[2]; > + real_to_target (res, > + CONST_DOUBLE_REAL_VALUE (value), > + REAL_MODE_FORMAT (mode)); > + > + ival = zext_hwi (res[needed - 1], 32); > + for (int i = needed - 2; i >= 0; i--) > + { > + ival <<= 32; > + ival |= zext_hwi (res[i], 32); > + } > + > + *intval = ival; > + return true; > +} > + > +/* Return TRUE if rtx X is an immediate constant that can be moved in > + created using a single MOV(+MOVK) followed by an FMOV. */ Typo. > +bool > +aarch64_float_const_rtx_p (rtx x) > +{ > + machine_mode mode = GET_MODE (x); > + if (mode == VOIDmode) > + return false; > + > + /* Determine whether it's cheaper to write float constants as > + mov/movk pairs over ldr/adrp pairs. */ > + unsigned HOST_WIDE_INT ival; > + > + if (GET_CODE (x) == CONST_DOUBLE > + && SCALAR_FLOAT_MODE_P (mode) > + && aarch64_reinterpret_float_as_int (x, &ival)) > + { > + machine_mode imode = mode == HFmode ? SImode : int_mode_for_mode (mode); > + int num_instr = aarch64_internal_mov_immediate > + (NULL_RTX, GEN_INT (ival), false, imode); Sorry to be a broken record on this, but since you explicitly zero-extend the real_to_target results from 32 bits, this will lead to an invalid 32-bit constant when the top bit of an SImode value is set, e.g. (const_int 0x8000_0000) instead of (const_int 0xffff_ffff_8000_0000). Using gen_int_mode would avoid this. In general it's better to use gen_int_mode instead of GEN_INT whenever the mode is known, to avoid this kind of corner case. There's another instance later in the patch. Thanks, Richard