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From: Richard Sandiford <rdsandiford@googlemail.com>
To: Sameera Deshpande <Sameera.Deshpande@imgtec.com>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>,
	 "gcc-patches\@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH][MIPS] Enable load-load/store-store bonding
Date: Mon, 23 Jun 2014 09:41:00 -0000	[thread overview]
Message-ID: <8761js6k15.fsf@talisman.default> (raw)
In-Reply-To: <38C8F1E431EDD94A82971C543A11B4FEE0BB2F@PUMAIL01.pu.imgtec.org>	(Sameera Deshpande's message of "Mon, 23 Jun 2014 09:17:55 +0000")

Sameera Deshpande <Sameera.Deshpande@imgtec.com> writes:
>> > +  if (TARGET_FIX_24K && TUNE_P5600)
>> > +    error ("unsupported combination: %s", "-mtune=p5600 -mfix-24k");
>> > +
>> >    /* Save the base compression state and process flags as though we
>> >       were generating uncompressed code.  */
>> >    mips_base_compression_flags = TARGET_COMPRESSION;
>> 
>> Although it's a bit of an odd combination, we need to accept -mfix-24k -
>> mtune=p5600 and continue to implement the 24k workarounds.
>> The idea is that a distributor can build for a common base architecture, add -
>> mfix- options for processors that might run the code, and add -mtune= for
>> the processor that's most of interest optimisation-wise.
>> 
>> We should just make the pairing of stores conditional on !TARGET_FIX_24K.
> We had offline discussion based on your comment. There is additional
> view on the same.
> Only ISAs mips32r2, mips32r3 and mips32r5 support P5600. Remaining ISAs
> do not support P5600.
> For mips32r2 (24K) and mips32r3 (micromips), load-store pairing is
> implemented separately, and hence, as you suggested, P5600 Ld-ST bonding
> optimization should not be enabled for them.
> So, is it fine if I emit error for any ISAs other than mips32r2,
> mips32r3 and mips32r5 when P5600 is enabled, or the compilation should
> continue by emitting warning and disabling P5600?

No, the point is that we have two separate concepts: ISA and optimisation
target.  -mipsN and -march=N control the ISA (which instructions are
available) and -mtune=M controls optimisation decisions within the
constraints of that N, such as scheduling and the cost of things like
multiplication and division.

E.g. you could have -mips2 -mtune=p5600 -mfix-24k: generate MIPS
II-compatible code, optimise it for p5600, but make sure that 24k
workarounds are used.  The code would run correctly on any MIPS
II-compatible processor without known errata and also on the 24k.

>> > +
>> > +#define ENABLE_LD_ST_PAIRING \
>> > +  (TARGET_ENABLE_LD_ST_PAIRING && TUNE_P5600)
>> 
>> The patch requires -mld-st-pairing to be passed explicitly even for -
>> mtune=p5600.  Is that because it's not a consistent enough win for us to
>> enable it by default?  It sounded from the description like it should be an
>> improvement more often that not.
>> 
>> We should allow pairing even without -mtune=p5600.
> Performance testing for this patch is not yet done. 
> If the patch proves beneficial in most of the testcases (which we
> believe will do on P5600) we will enable this optimization by default
> for P5600 - in which case this option can be removed.

OK.  Sending the patch for comments before performance testing is fine,
but I think it'd be better to commit the patch only after the testing
is done, since otherwise the patch might need to be tweaked.

I don't see any problem with keeping the option in case people want to
experiment with it.  I just think the patch should only go in once it
can be enabled by default for p5600.  I.e. the option would exist to
turn off the pairing.

Not having the option is fine too of course.

>> Are QImodes not paired in the same way?  If so, it'd be worth adding a
>> comment above the define_mode_iterator saying that QI is deliberately
>> excluded.
> The P5600 datasheet mentions bonding of load/stores in HI, SI, SF and DF
> modes only. Hence QI mode is excluded. I will add the comment on the
> iterator.

Thanks.

Richard

  reply	other threads:[~2014-06-23  9:41 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <38C8F1E431EDD94A82971C543A11B4FEE0A588@PUMAIL01.pu.imgtec.org>
2014-06-21 16:25 ` Richard Sandiford
2014-06-23  9:18   ` Sameera Deshpande
2014-06-23  9:41     ` Richard Sandiford [this message]
2014-06-24 10:42   ` Sameera Deshpande
2015-03-30 11:28     ` sameera
2015-04-20  5:09       ` sameera
2015-04-20 18:30         ` Mike Stump
2015-04-20 19:09         ` Matthew Fortune
2015-04-20 22:01           ` Moore, Catherine
2015-05-11 11:05           ` sameera
2015-05-11 12:13             ` Matthew Fortune
2015-05-11 12:39               ` sameera
2015-05-11 16:40             ` Mike Stump
2015-05-13  7:39               ` sameera
2014-06-19  9:41 Sameera Deshpande

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