From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id D85B23858D32 for ; Wed, 19 Jul 2023 06:43:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D85B23858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J6eSo7011485; Wed, 19 Jul 2023 06:43:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=T9PpMMfLy5T6voBWijjoHEq6XAmgAXn/EetKMa1mUto=; b=qRrojF66JVvb4Xg6TZkNbr62cNE3/a8LjVVTQEkqDKVs66wa7vTHXG3IMXbb99xRPoTz HKLZC3FU5lHsgieF0idFOsu1pXjAvycOQKd51xCDiz7s76fTDZ4v3xwdHZF5K5en9CET 4APBX4JzapG37rvKm8lSQ/Ji17TVPVooe797Kp57S8xwR0OYGXTwGhbg1cAprC50A+ZU m+QbucLHgUhX9NYa4mY0OzYK1sDsJuP5VdOupyB1VaMYFA0C3VZaGTJD9bGc8+sungcI Z1CPEGeVJUYeIzSJ48l5KNUIXpH2obgnhRtyvqr3WNL0TgO8WrbmYN1/Lhwm2hqNh99F Cw== Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rx6hcctr0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 06:43:26 +0000 Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 36J410xg005272; Wed, 19 Jul 2023 06:43:25 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3rv65xgdep-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 06:43:25 +0000 Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 36J6hNHP44761552 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 19 Jul 2023 06:43:23 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1D30420040; Wed, 19 Jul 2023 06:43:23 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4147220043; Wed, 19 Jul 2023 06:43:21 +0000 (GMT) Received: from [9.177.7.147] (unknown [9.177.7.147]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 19 Jul 2023 06:43:20 +0000 (GMT) Message-ID: <87733c19-c853-a6c8-7133-61ac42245518@linux.ibm.com> Date: Wed, 19 Jul 2023 14:43:19 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH V2] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320] Content-Language: en-US To: P Jeevitha Cc: Peter Bergner , Segher Boessenkool , gcc-patches@gcc.gnu.org References: <99f9935c-5430-dcd7-1235-ccad50fb6122@linux.vnet.ibm.com> From: "Kewen.Lin" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jGCPrCmrEI4uMD6Dc9UzZcIZa-pMf1pq X-Proofpoint-ORIG-GUID: jGCPrCmrEI4uMD6Dc9UzZcIZa-pMf1pq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_03,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 adultscore=0 malwarescore=0 impostorscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190061 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Jeevitha, on 2023/7/17 11:40, P Jeevitha wrote: > > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. Since one line touched has (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) and powerpc64le-linux only adopts ABI_ELFv2, could you also test this on powerpc64-linux or aix to ensure it doesn't break ABI_AIX as we expected? And Peter made the diff on rs6000.cc, I guess you want to put him as co-author, i.e maybe adding one line with: Co-authored-by: Peter Bergner The others look good to me, okay for trunk if the suggested testings go well as expected. Thanks! BR, Kewen > > Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile > register. However, it can be used as volatile for PCREL addressing. Therefore, > modified r2 to be non-fixed in FIXED_REGISTERS and set it to fixed if it is not > PCREL and also when the user explicitly requests TOC or fixed. If the register > r2 is fixed, it is made as non-volatile. Changes in register preservation roles > can be accomplished with the help of available target hooks > (TARGET_CONDITIONAL_REGISTER_USAGE). > > 2023-07-12 Jeevitha Palanisamy > > gcc/ > PR target/PR110320 > * config/rs6000/rs6000.cc (rs6000_conditional_register_usage): Change > GPR2 to volatile and non-fixed register for PCREL. > > gcc/testsuite/ > PR target/PR110320 > * gcc.target/powerpc/pr110320-1.c: New testcase. > * gcc.target/powerpc/pr110320-2.c: New testcase. > * gcc.target/powerpc/pr110320-3.c: New testcase. > > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index 44b448d2ba6..9aa04ec5d57 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -10193,9 +10193,13 @@ rs6000_conditional_register_usage (void) > for (i = 32; i < 64; i++) > fixed_regs[i] = call_used_regs[i] = 1; > > + /* For non PC-relative code, GPR2 is unavailable for register allocation. */ > + if (FIXED_R2 && !rs6000_pcrel_p ()) > + fixed_regs[2] = 1; > + > /* The TOC register is not killed across calls in a way that is > visible to the compiler. */ > - if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) > + if (fixed_regs[2] && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)) > call_used_regs[2] = 0; > > if (DEFAULT_ABI == ABI_V4 && flag_pic == 2) > diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h > index 3503614efbd..2a24fbdf9fd 100644 > --- a/gcc/config/rs6000/rs6000.h > +++ b/gcc/config/rs6000/rs6000.h > @@ -812,7 +812,7 @@ enum data_align { align_abi, align_opt, align_both }; > > #define FIXED_REGISTERS \ > {/* GPRs */ \ > - 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ > + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ > 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ > /* FPRs */ \ > 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ > diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-1.c b/gcc/testsuite/gcc.target/powerpc/pr110320-1.c > new file mode 100644 > index 00000000000..a4ad34d9303 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr110320-1.c > @@ -0,0 +1,22 @@ > +/* PR target/110320 */ > +/* { dg-require-effective-target powerpc_pcrel } */ > +/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ > + > +/* Ensure we use r2 as a normal volatile register for the code below. > + The test case ensures all of the parameter registers r3 - r10 are used > + and needed after we compute the expression "x + y" which requires a > + temporary. The -ffixed-r* options disallow using the other volatile > + registers r0, r11 and r12. That leaves RA to choose from r2 and the more > + expensive non-volatile registers for the temporary to be assigned to, and > + RA will always chooses the cheaper volatile r2 register. */ > + > +extern long bar (long, long, long, long, long, long, long, long *); > + > +long > +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) > +{ > + *r10 = r3 + r4; > + return bar (r3, r4, r5, r6, r7, r8, r9, r10); > +} > + > +/* { dg-final { scan-assembler {\madd 2,3,4\M} } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-2.c b/gcc/testsuite/gcc.target/powerpc/pr110320-2.c > new file mode 100644 > index 00000000000..9d6aefedd2e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr110320-2.c > @@ -0,0 +1,21 @@ > +/* PR target/110320 */ > +/* { dg-require-effective-target powerpc_pcrel } */ > +/* { dg-options "-O2 -mdejagnu-cpu=power10 -mno-pcrel -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ > + > +/* Ensure we don't use r2 as a normal volatile register for the code below. > + The test case ensures all of the parameter registers r3 - r10 are used > + and needed after we compute the expression "x + y" which requires a > + temporary. The -ffixed-r* options disallow using the other volatile > + registers r0, r11 and r12. That only leaves RA to choose from the more > + expensive non-volatile registers for the temporary to be assigned to. */ > + > +extern long bar (long, long, long, long, long, long, long, long *); > + > +long > +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) > +{ > + *r10 = r3 + r4; > + return bar (r3, r4, r5, r6, r7, r8, r9, r10); > +} > + > +/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-3.c b/gcc/testsuite/gcc.target/powerpc/pr110320-3.c > new file mode 100644 > index 00000000000..ea6c6188c8d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr110320-3.c > @@ -0,0 +1,21 @@ > +/* PR target/110320 */ > +/* { dg-require-effective-target powerpc_pcrel } */ > +/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r2 -ffixed-r11 -ffixed-r12" } */ > + > +/* Ensure we don't use r2 as a normal volatile register for the code below. > + The test case ensures all of the parameter registers r3 - r10 are used > + and needed after we compute the expression "x + y" which requires a > + temporary. The -ffixed-r* options disallow using the other volatile > + registers r0, r2, r11 and r12. That only leaves RA to choose from the more > + expensive non-volatile registers for the temporary to be assigned to. */ > + > +extern long bar (long, long, long, long, long, long, long, long *); > + > +long > +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) > +{ > + *r10 = r3 + r4; > + return bar (r3, r4, r5, r6, r7, r8, r9, r10); > +} > + > +/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */ > >