From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by sourceware.org (Postfix) with ESMTPS id 6A7CD386F006 for ; Mon, 18 Jan 2021 16:06:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6A7CD386F006 Received: by mail-pf1-x42b.google.com with SMTP id t29so5322798pfg.11 for ; Mon, 18 Jan 2021 08:06:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:user-agent:to:subject:message-id:date :mime-version; bh=xclM0yRkWOTEHajIvWvuniCRZEgNBBx5KcQy9K7CpTA=; b=mV2BRjNBLqAUGRgFcgxbK+vaY31ddIJj5Usu4sKfc45QiBsxQXJFqqecwdyNNUxpty Q2qky0BOeHfRSCOrXG53eJvrLchS1m7gnjG1MgFN9yPSyyedeDS18e/2vA122W4D0NOS sxBLy9ZYGIIvHeDswIsL5hepfQhWLYC3qXgCiv13QU3hpUTjvcU0gvdF+ANrMrblwtrL o3mfwIruHyrmyGbR0Dz9Tk8RaKEIHVNZWpZxCP5+aR7DVMXdfX3VP0PAuFgQlDO82l5e 7tT2AFlwMIdWWThLMlEDnLmEm59RlPi2QwJZXqcxNMDthNNCKuEdVGvfiauT1LgaGxar XK/A== X-Gm-Message-State: AOAM532wNFZy159GEOS0BPTHMLUzPtTRjqrGsbjGDdlZ8GLk0cMmJmMH ENXlfasho1pdJ+zuz18JvOBEGWnri+naUw== X-Google-Smtp-Source: ABdhPJxChEmLdQ+Iq2FR6+S8Mga+4ETSyw0//9gvC4Zp6Tx5gcb85D4wJ03Vn/JWOpomoAwLxVJzRw== X-Received: by 2002:a63:af50:: with SMTP id s16mr354169pgo.448.1610986015162; Mon, 18 Jan 2021 08:06:55 -0800 (PST) Received: from nightfury ([2401:4900:173e:b58d:cea:4a8f:c01:75de]) by smtp.gmail.com with ESMTPSA id o14sm3096862pjf.12.2021.01.18.08.06.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 08:06:54 -0800 (PST) From: Senthil Kumar Selvaraj X-Google-Original-From: Senthil Kumar Selvaraj User-agent: mu4e 1.4.13; emacs 27.1 To: gcc-patches@gcc.gnu.org, avr@gjlay.de, chertykov@gmail.com Subject: [PATCH 2/n] AVR CC0 conversion - adjust peepholes Message-ID: <87a6t6p6uh.fsf@gcc.gnu.org> Date: Mon, 18 Jan 2021 21:36:46 +0530 MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 16:06:59 -0000 Hi, This patch, to be applied on top of https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html, adjusts peepholes to match and generate parallels with a clobber of REG_CC. It also sets mov_insn as the name of the pattern for the split insn (rather than the define_insn_and_split), so that avr_2word_insn_p, which looks for CODE_FOR_mov_insn, works correctly. This is required for the *cpse.eq peephole to fire, and also helps generate better code for avr_out_sbxx_branch. There are no regressions, and the number of test cases reporting UNSUPPORTED or FAIL because of code size changes (when compared to mainline) for attiny40 and atmega8 are now down to 3 and 3, respectively, from 10 and 25 previously. The embench-iot numbers also show a good improvement. Benchmark Baseline Current Increase % --------- ---- ------- ------ aha-mont64 6,944 6,944 0 crc32 704 706 0.28 cubic 9,428 9,428 0 edn 3,854 3,854 0 huffbench 2,890 2,890 0 matmult-int 1,164 1,164 0 minver 3,960 3,956 -0.1 nbody 3,106 3,110 0.13 nettle-aes 5,292 5,304 0.23 nettle-sha256 25,748 25,748 0 nsichneu 39,622 39,622 0 picojpeg 9,898 9,980 0.83 qrduino 9,234 9,356 1.32 sglib-combined 4,658 4,658 0 slre 4,000 4,000 0 st 3,356 3,356 0 statemate 5,490 5,502 0.22 ud 2,940 2,940 0 wikisort 20,776 20,772 -0.02 Regards Senthil gcc/ChangeLog: * config/avr/avr.md: Adjust peepholes to match and generate parallels with clobber of REG_CC. (mov_insn): Rename to mov_insn_split. (*mov_insn): Rename to mov_insn. diff --git gcc/config/avr/avr.md gcc/config/avr/avr.md index 2206fa19671..a1a325b7a8c 100644 --- gcc/config/avr/avr.md +++ gcc/config/avr/avr.md @@ -724,9 +724,7 @@ (define_expand "mov" ;; are call-saved registers, and most of LD_REGS are call-used registers, ;; so this may still be a win for registers live across function calls. -;; "movqi_insn" -;; "movqq_insn" "movuqq_insn" -(define_insn_and_split "mov_insn" +(define_insn_and_split "mov_insn_split" [(set (match_operand:ALL1 0 "nonimmediate_operand" "=r ,d ,Qm ,r ,q,r,*r") (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i"))] "register_operand (operands[0], mode) @@ -737,7 +735,9 @@ (define_insn_and_split "mov_insn" (match_dup 1)) (clobber (reg:CC REG_CC))])]) -(define_insn "*mov_insn" +;; "movqi_insn" +;; "movqq_insn" "movuqq_insn" +(define_insn "mov_insn" [(set (match_operand:ALL1 0 "nonimmediate_operand" "=r ,d ,Qm ,r ,q,r,*r") (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i")) (clobber (reg:CC REG_CC))] @@ -758,7 +758,8 @@ (define_insn "*mov_insn" (define_insn "*reload_in" [(set (match_operand:ALL1 0 "register_operand" "=l") (match_operand:ALL1 1 "const_operand" "i")) - (clobber (match_operand:QI 2 "register_operand" "=&d"))] + (clobber (match_operand:QI 2 "register_operand" "=&d")) + (clobber (reg:CC REG_CC))] "reload_completed" "ldi %2,lo8(%1) mov %0,%2" @@ -766,15 +767,17 @@ (define_insn "*reload_in" (define_peephole2 [(match_scratch:QI 2 "d") - (set (match_operand:ALL1 0 "l_register_operand" "") - (match_operand:ALL1 1 "const_operand" ""))] + (parallel [(set (match_operand:ALL1 0 "l_register_operand" "") + (match_operand:ALL1 1 "const_operand" "")) + (clobber (reg:CC REG_CC))])] ; No need for a clobber reg for 0x0, 0x01 or 0xff "!satisfies_constraint_Y00 (operands[1]) && !satisfies_constraint_Y01 (operands[1]) && !satisfies_constraint_Ym1 (operands[1])" [(parallel [(set (match_dup 0) (match_dup 1)) - (clobber (match_dup 2))])]) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])]) ;;============================================================================ ;; move word (16 bit) @@ -804,12 +807,14 @@ (define_insn "movhi_sp_r" (define_peephole2 [(match_scratch:QI 2 "d") - (set (match_operand:ALL2 0 "l_register_operand" "") - (match_operand:ALL2 1 "const_or_immediate_operand" ""))] + (parallel [(set (match_operand:ALL2 0 "l_register_operand" "") + (match_operand:ALL2 1 "const_or_immediate_operand" "")) + (clobber (reg:CC REG_CC))])] "operands[1] != CONST0_RTX (mode)" [(parallel [(set (match_dup 0) (match_dup 1)) - (clobber (match_dup 2))])]) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])]) ;; '*' because it is not used in rtl generation, only in above peephole ;; "*reload_inhi" @@ -855,30 +860,36 @@ (define_insn "*mov" (set_attr "adjust_len" "mov16")]) (define_peephole2 ; movw - [(set (match_operand:ALL1 0 "even_register_operand" "") - (match_operand:ALL1 1 "even_register_operand" "")) - (set (match_operand:ALL1 2 "odd_register_operand" "") - (match_operand:ALL1 3 "odd_register_operand" ""))] + [(parallel [(set (match_operand:ALL1 0 "even_register_operand" "") + (match_operand:ALL1 1 "even_register_operand" "")) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_operand:ALL1 2 "odd_register_operand" "") + (match_operand:ALL1 3 "odd_register_operand" "")) + (clobber (reg:CC REG_CC))])] "AVR_HAVE_MOVW && REGNO (operands[0]) == REGNO (operands[2]) - 1 && REGNO (operands[1]) == REGNO (operands[3]) - 1" - [(set (match_dup 4) - (match_dup 5))] + [(parallel [(set (match_dup 4) + (match_dup 5)) + (clobber (reg:CC REG_CC))])] { operands[4] = gen_rtx_REG (HImode, REGNO (operands[0])); operands[5] = gen_rtx_REG (HImode, REGNO (operands[1])); }) (define_peephole2 ; movw_r - [(set (match_operand:ALL1 0 "odd_register_operand" "") - (match_operand:ALL1 1 "odd_register_operand" "")) - (set (match_operand:ALL1 2 "even_register_operand" "") - (match_operand:ALL1 3 "even_register_operand" ""))] + [(parallel [(set (match_operand:ALL1 0 "odd_register_operand" "") + (match_operand:ALL1 1 "odd_register_operand" "")) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_operand:ALL1 2 "even_register_operand" "") + (match_operand:ALL1 3 "even_register_operand" "")) + (clobber (reg:CC REG_CC))])] "AVR_HAVE_MOVW && REGNO (operands[2]) == REGNO (operands[0]) - 1 && REGNO (operands[3]) == REGNO (operands[1]) - 1" - [(set (match_dup 4) - (match_dup 5))] + [(parallel [(set (match_dup 4) + (match_dup 5)) + (clobber (reg:CC REG_CC))])] { operands[4] = gen_rtx_REG (HImode, REGNO (operands[2])); operands[5] = gen_rtx_REG (HImode, REGNO (operands[3])); @@ -919,8 +930,9 @@ (define_split ; "split-lpmx" (define_peephole2 ; *reload_inpsi [(match_scratch:QI 2 "d") - (set (match_operand:PSI 0 "l_register_operand" "") - (match_operand:PSI 1 "immediate_operand" "")) + (parallel [(set (match_operand:PSI 0 "l_register_operand" "") + (match_operand:PSI 1 "immediate_operand" "")) + (clobber (reg:CC REG_CC))]) (match_dup 2)] "operands[1] != const0_rtx && operands[1] != constm1_rtx" @@ -973,8 +985,9 @@ (define_insn "*movpsi" (define_peephole2 ; *reload_insi [(match_scratch:QI 2 "d") - (set (match_operand:ALL4 0 "l_register_operand" "") - (match_operand:ALL4 1 "immediate_operand" "")) + (parallel [(set (match_operand:ALL4 0 "l_register_operand" "") + (match_operand:ALL4 1 "immediate_operand" "")) + (clobber (reg:CC REG_CC))]) (match_dup 2)] "operands[1] != CONST0_RTX (mode)" [(parallel [(set (match_dup 0) @@ -1055,8 +1068,9 @@ (define_insn "*movsf" (define_peephole2 ; *reload_insf [(match_scratch:QI 2 "d") - (set (match_operand:SF 0 "l_register_operand" "") - (match_operand:SF 1 "const_double_operand" "")) + (parallel [(set (match_operand:SF 0 "l_register_operand" "") + (match_operand:SF 1 "const_double_operand" "")) + (clobber (reg:CC REG_CC))]) (match_dup 2)] "operands[1] != CONST0_RTX (SFmode)" [(parallel [(set (match_dup 0) @@ -1603,16 +1617,19 @@ (define_insn "*add3" ;; itself because that insn is special to reload. (define_peephole2 ; addhi3_clobber - [(set (match_operand:ALL2 0 "d_register_operand" "") - (match_operand:ALL2 1 "const_operand" "")) - (set (match_operand:ALL2 2 "l_register_operand" "") - (plus:ALL2 (match_dup 2) - (match_dup 0)))] + [(parallel [(set (match_operand:ALL2 0 "d_register_operand" "") + (match_operand:ALL2 1 "const_operand" "")) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_operand:ALL2 2 "l_register_operand" "") + (plus:ALL2 (match_dup 2) + (match_dup 0))) + (clobber (reg:CC REG_CC))])] "peep2_reg_dead_p (2, operands[0])" [(parallel [(set (match_dup 2) (plus:ALL2 (match_dup 2) (match_dup 1))) - (clobber (match_dup 3))])] + (clobber (match_dup 3)) + (clobber (reg:CC REG_CC))])] { operands[3] = simplify_gen_subreg (QImode, operands[0], mode, 0); }) @@ -1623,15 +1640,18 @@ (define_peephole2 ; addhi3_clobber (define_peephole2 ; addhi3_clobber [(parallel [(set (match_operand:ALL2 0 "l_register_operand" "") (match_operand:ALL2 1 "const_operand" "")) - (clobber (match_operand:QI 2 "d_register_operand" ""))]) - (set (match_operand:ALL2 3 "l_register_operand" "") - (plus:ALL2 (match_dup 3) - (match_dup 0)))] + (clobber (match_operand:QI 2 "d_register_operand" "")) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_operand:ALL2 3 "l_register_operand" "") + (plus:ALL2 (match_dup 3) + (match_dup 0))) + (clobber (reg:CC REG_CC))])] "peep2_reg_dead_p (2, operands[0])" [(parallel [(set (match_dup 3) (plus:ALL2 (match_dup 3) (match_dup 1))) - (clobber (match_dup 2))])]) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])]) ;; "addhi3_clobber" ;; "addhq3_clobber" "adduhq3_clobber" @@ -4387,14 +4407,17 @@ (define_insn "*andsi3" (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")]) (define_peephole2 ; andi - [(set (match_operand:QI 0 "d_register_operand" "") - (and:QI (match_dup 0) - (match_operand:QI 1 "const_int_operand" ""))) - (set (match_dup 0) - (and:QI (match_dup 0) - (match_operand:QI 2 "const_int_operand" "")))] + [(parallel [(set (match_operand:QI 0 "d_register_operand" "") + (and:QI (match_dup 0) + (match_operand:QI 1 "const_int_operand" ""))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (and:QI (match_dup 0) + (match_operand:QI 2 "const_int_operand" ""))) + (clobber (reg:CC REG_CC))])] "" - [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))] + [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) + (clobber (reg:CC REG_CC))])] { operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2])); }) @@ -5140,13 +5163,15 @@ (define_insn_and_split "*ashlhiqi3" ;; No need to compute it, map to 8-bit shift. (define_peephole2 - [(set (match_operand:HI 0 "register_operand" "") - (ashift:HI (match_dup 0) - (match_operand:QI 1 "register_operand" "")))] + [(parallel [(set (match_operand:HI 0 "register_operand" "") + (ashift:HI (match_dup 0) + (match_operand:QI 1 "register_operand" ""))) + (clobber (reg:CC REG_CC))])] "" - [(set (match_dup 2) - (ashift:QI (match_dup 2) - (match_dup 1))) + [(parallel [(set (match_dup 2) + (ashift:QI (match_dup 2) + (match_dup 1))) + (clobber (reg:CC REG_CC))]) (clobber (match_dup 3))] { operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 1); @@ -5188,56 +5213,72 @@ (define_insn "*ashl3" ;; Optimize if a scratch register from LD_REGS happens to be available. (define_peephole2 ; ashlqi3_l_const4 - [(set (match_operand:ALL1 0 "l_register_operand" "") - (ashift:ALL1 (match_dup 0) - (const_int 4))) + [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "") + (ashift:ALL1 (match_dup 0) + (const_int 4))) + (clobber (reg:CC REG_CC))]) (match_scratch:QI 1 "d")] "" - [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) - (set (match_dup 1) (const_int -16)) - (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))] + [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 1) (const_int -16)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1))) + (clobber (reg:CC REG_CC))])] { operands[2] = avr_to_int_mode (operands[0]); }) (define_peephole2 ; ashlqi3_l_const5 - [(set (match_operand:ALL1 0 "l_register_operand" "") - (ashift:ALL1 (match_dup 0) - (const_int 5))) + [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "") + (ashift:ALL1 (match_dup 0) + (const_int 5))) + (clobber (reg:CC REG_CC))]) (match_scratch:QI 1 "d")] "" - [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) - (set (match_dup 2) (ashift:QI (match_dup 2) (const_int 1))) - (set (match_dup 1) (const_int -32)) - (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))] + [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (ashift:QI (match_dup 2) (const_int 1))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 1) (const_int -32)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1))) + (clobber (reg:CC REG_CC))])] { operands[2] = avr_to_int_mode (operands[0]); }) (define_peephole2 ; ashlqi3_l_const6 - [(set (match_operand:ALL1 0 "l_register_operand" "") - (ashift:ALL1 (match_dup 0) - (const_int 6))) + [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "") + (ashift:ALL1 (match_dup 0) + (const_int 6))) + (clobber (reg:CC REG_CC))]) (match_scratch:QI 1 "d")] "" - [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) - (set (match_dup 2) (ashift:QI (match_dup 2) (const_int 2))) - (set (match_dup 1) (const_int -64)) - (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))] + [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (ashift:QI (match_dup 2) (const_int 2))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 1) (const_int -64)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1))) + (clobber (reg:CC REG_CC))])] { operands[2] = avr_to_int_mode (operands[0]); }) (define_peephole2 [(match_scratch:QI 3 "d") - (set (match_operand:ALL2 0 "register_operand" "") - (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "") - (match_operand:QI 2 "const_int_operand" "")))] + (parallel [(set (match_operand:ALL2 0 "register_operand" "") + (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "") + (match_operand:QI 2 "const_int_operand" ""))) + (clobber (reg:CC REG_CC))])] "" [(parallel [(set (match_dup 0) (ashift:ALL2 (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))])]) + (clobber (match_dup 3)) + (clobber (reg:CC REG_CC))])]) ;; "*ashlhi3_const" ;; "*ashlhq3_const" "*ashluhq3_const" @@ -5271,14 +5312,16 @@ (define_insn "*ashl3_const" (define_peephole2 [(match_scratch:QI 3 "d") - (set (match_operand:ALL4 0 "register_operand" "") - (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "") - (match_operand:QI 2 "const_int_operand" "")))] + (parallel [(set (match_operand:ALL4 0 "register_operand" "") + (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "") + (match_operand:QI 2 "const_int_operand" ""))) + (clobber (reg:CC REG_CC))])] "" [(parallel [(set (match_dup 0) (ashift:ALL4 (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))])]) + (clobber (match_dup 3)) + (clobber (reg:CC REG_CC))])]) ;; "*ashlsi3_const" ;; "*ashlsq3_const" "*ashlusq3_const" @@ -5476,14 +5519,16 @@ (define_insn "*ashr3" (define_peephole2 [(match_scratch:QI 3 "d") - (set (match_operand:ALL2 0 "register_operand" "") - (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "") - (match_operand:QI 2 "const_int_operand" "")))] + (parallel [(set (match_operand:ALL2 0 "register_operand" "") + (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "") + (match_operand:QI 2 "const_int_operand" ""))) + (clobber (reg:CC REG_CC))])] "" [(parallel [(set (match_dup 0) (ashiftrt:ALL2 (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))])]) + (clobber (match_dup 3)) + (clobber (reg:CC REG_CC))])]) ;; "*ashrhi3_const" ;; "*ashrhq3_const" "*ashruhq3_const" @@ -5517,14 +5562,16 @@ (define_insn "*ashr3_const" (define_peephole2 [(match_scratch:QI 3 "d") - (set (match_operand:ALL4 0 "register_operand" "") - (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "") - (match_operand:QI 2 "const_int_operand" "")))] + (parallel [(set (match_operand:ALL4 0 "register_operand" "") + (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "") + (match_operand:QI 2 "const_int_operand" ""))) + (clobber (reg:CC REG_CC))])] "" [(parallel [(set (match_dup 0) (ashiftrt:ALL4 (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))])]) + (clobber (match_dup 3)) + (clobber (reg:CC REG_CC))])]) ;; "*ashrsi3_const" ;; "*ashrsq3_const" "*ashrusq3_const" @@ -5715,56 +5762,72 @@ (define_insn "*lshr3" ;; Optimize if a scratch register from LD_REGS happens to be available. (define_peephole2 ; lshrqi3_l_const4 - [(set (match_operand:ALL1 0 "l_register_operand" "") - (lshiftrt:ALL1 (match_dup 0) - (const_int 4))) + [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "") + (lshiftrt:ALL1 (match_dup 0) + (const_int 4))) + (clobber (reg:CC REG_CC))]) (match_scratch:QI 1 "d")] "" - [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) - (set (match_dup 1) (const_int 15)) - (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))] + [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 1) (const_int 15)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1))) + (clobber (reg:CC REG_CC))])] { operands[2] = avr_to_int_mode (operands[0]); }) (define_peephole2 ; lshrqi3_l_const5 - [(set (match_operand:ALL1 0 "l_register_operand" "") - (lshiftrt:ALL1 (match_dup 0) - (const_int 5))) + [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "") + (lshiftrt:ALL1 (match_dup 0) + (const_int 5))) + (clobber (reg:CC REG_CC))]) (match_scratch:QI 1 "d")] "" - [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) - (set (match_dup 2) (lshiftrt:QI (match_dup 2) (const_int 1))) - (set (match_dup 1) (const_int 7)) - (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))] + [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (lshiftrt:QI (match_dup 2) (const_int 1))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 1) (const_int 7)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1))) + (clobber (reg:CC REG_CC))])] { operands[2] = avr_to_int_mode (operands[0]); }) (define_peephole2 ; lshrqi3_l_const6 - [(set (match_operand:ALL1 0 "l_register_operand" "") - (lshiftrt:ALL1 (match_dup 0) - (const_int 6))) + [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "") + (lshiftrt:ALL1 (match_dup 0) + (const_int 6))) + (clobber (reg:CC REG_CC))]) (match_scratch:QI 1 "d")] "" - [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) - (set (match_dup 2) (lshiftrt:QI (match_dup 2) (const_int 2))) - (set (match_dup 1) (const_int 3)) - (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))] + [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (lshiftrt:QI (match_dup 2) (const_int 2))) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 1) (const_int 3)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1))) + (clobber (reg:CC REG_CC))])] { operands[2] = avr_to_int_mode (operands[0]); }) (define_peephole2 [(match_scratch:QI 3 "d") - (set (match_operand:ALL2 0 "register_operand" "") - (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "") - (match_operand:QI 2 "const_int_operand" "")))] + (parallel [(set (match_operand:ALL2 0 "register_operand" "") + (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "") + (match_operand:QI 2 "const_int_operand" ""))) + (clobber (reg:CC REG_CC))])] "" [(parallel [(set (match_dup 0) (lshiftrt:ALL2 (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))])]) + (clobber (match_dup 3)) + (clobber (reg:CC REG_CC))])]) ;; "*lshrhi3_const" ;; "*lshrhq3_const" "*lshruhq3_const" @@ -5798,14 +5861,16 @@ (define_insn "*lshr3_const" (define_peephole2 [(match_scratch:QI 3 "d") - (set (match_operand:ALL4 0 "register_operand" "") - (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "") - (match_operand:QI 2 "const_int_operand" "")))] + (parallel [(set (match_operand:ALL4 0 "register_operand" "") + (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "") + (match_operand:QI 2 "const_int_operand" ""))) + (clobber (reg:CC REG_CC))])] "" [(parallel [(set (match_dup 0) (lshiftrt:ALL4 (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))])]) + (clobber (match_dup 3)) + (clobber (reg:CC REG_CC))])]) ;; "*lshrsi3_const" ;; "*lshrsq3_const" "*lshrusq3_const" @@ -6817,83 +6882,95 @@ (define_insn "*sbrx_and_branch" (define_peephole2 [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "") (const_int 0))) - (set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) - (label_ref (match_operand 1 "" "")) - (pc)))] + (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" - [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0) - (const_int 1) - (const_int 7)) - (const_int 0)) - (label_ref (match_dup 1)) - (pc)))]) + [(parallel [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0) + (const_int 1) + (const_int 7)) + (const_int 0)) + (label_ref (match_dup 1)) + (pc))) + (clobber (reg:CC REG_CC))])]) (define_peephole2 [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "") (const_int 0))) - (set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) - (label_ref (match_operand 1 "" "")) - (pc)))] + (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" - [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0) - (const_int 1) - (const_int 7)) - (const_int 0)) - (label_ref (match_dup 1)) - (pc)))]) + [(parallel [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0) + (const_int 1) + (const_int 7)) + (const_int 0)) + (label_ref (match_dup 1)) + (pc))) + (clobber (reg:CC REG_CC))])]) (define_peephole2 [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "") (const_int 0))) (clobber (match_operand:HI 2 ""))]) - (set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) - (label_ref (match_operand 1 "" "")) - (pc)))] + (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" - [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768)) - (const_int 0)) - (label_ref (match_dup 1)) - (pc)))]) + [(parallel [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768)) + (const_int 0)) + (label_ref (match_dup 1)) + (pc))) + (clobber (reg:CC REG_CC))])]) (define_peephole2 [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "") (const_int 0))) (clobber (match_operand:HI 2 ""))]) - (set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) - (label_ref (match_operand 1 "" "")) - (pc)))] + (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" - [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768)) - (const_int 0)) - (label_ref (match_dup 1)) - (pc)))]) + [(parallel [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768)) + (const_int 0)) + (label_ref (match_dup 1)) + (pc))) + (clobber (reg:CC REG_CC))])]) (define_peephole2 [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "") (const_int 0))) (clobber (match_operand:SI 2 ""))]) - (set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) - (label_ref (match_operand 1 "" "")) - (pc)))] - "" - [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2)) - (const_int 0)) - (label_ref (match_dup 1)) - (pc)))] + (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] + "" + [(parallel [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2)) + (const_int 0)) + (label_ref (match_dup 1)) + (pc))) + (clobber (reg:CC REG_CC))])] "operands[2] = gen_int_mode (-2147483647 - 1, SImode);") (define_peephole2 [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "") (const_int 0))) (clobber (match_operand:SI 2 ""))]) - (set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) - (label_ref (match_operand 1 "" "")) - (pc)))] - "" - [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2)) - (const_int 0)) - (label_ref (match_dup 1)) - (pc)))] + (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] + "" + [(parallel [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2)) + (const_int 0)) + (label_ref (match_dup 1)) + (pc))) + (clobber (reg:CC REG_CC))])] "operands[2] = gen_int_mode (-2147483647 - 1, SImode);") ;; ************************************************************************ @@ -7575,16 +7652,18 @@ (define_peephole ; "*dec-and-branchsi!=-1.d.clobber" [(parallel [(set (match_operand:SI 0 "d_register_operand" "") (plus:SI (match_dup 0) (const_int -1))) - (clobber (scratch:QI))]) + (clobber (scratch:QI)) + (clobber (reg:CC REG_CC))]) (parallel [(set (reg:CC REG_CC) (compare:CC (match_dup 0) (const_int -1))) (clobber (match_operand:QI 1 "d_register_operand" ""))]) - (set (pc) - (if_then_else (eqne (reg:CC REG_CC) - (const_int 0)) - (label_ref (match_operand 2 "" "")) - (pc)))] + (parallel [(set (pc) + (if_then_else (eqne (reg:CC REG_CC) + (const_int 0)) + (label_ref (match_operand 2 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" { const char *op; @@ -7616,18 +7695,20 @@ (define_peephole ; "*dec-and-branchsi!=-1.d.clobber" }) (define_peephole ; "*dec-and-branchhi!=-1" - [(set (match_operand:HI 0 "d_register_operand" "") - (plus:HI (match_dup 0) - (const_int -1))) + [(parallel [(set (match_operand:HI 0 "d_register_operand" "") + (plus:HI (match_dup 0) + (const_int -1))) + (clobber (reg:CC REG_CC))]) (parallel [(set (reg:CC REG_CC) (compare:CC (match_dup 0) (const_int -1))) (clobber (match_operand:QI 1 "d_register_operand" ""))]) - (set (pc) - (if_then_else (eqne (reg:CC REG_CC) - (const_int 0)) - (label_ref (match_operand 2 "" "")) - (pc)))] + (parallel [(set (pc) + (if_then_else (eqne (reg:CC REG_CC) + (const_int 0)) + (label_ref (match_operand 2 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" { const char *op; @@ -7659,16 +7740,18 @@ (define_peephole ; "*dec-and-branchhi!=-1.d.clobber" [(parallel [(set (match_operand:HI 0 "d_register_operand" "") (plus:HI (match_dup 0) (const_int -1))) - (clobber (scratch:QI))]) + (clobber (scratch:QI)) + (clobber (reg:CC REG_CC))]) (parallel [(set (reg:CC REG_CC) (compare:CC (match_dup 0) (const_int -1))) (clobber (match_operand:QI 1 "d_register_operand" ""))]) - (set (pc) - (if_then_else (eqne (reg:CC REG_CC) - (const_int 0)) - (label_ref (match_operand 2 "" "")) - (pc)))] + (parallel [(set (pc) + (if_then_else (eqne (reg:CC REG_CC) + (const_int 0)) + (label_ref (match_operand 2 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" { const char *op; @@ -7700,16 +7783,18 @@ (define_peephole ; "*dec-and-branchhi!=-1.l.clobber" [(parallel [(set (match_operand:HI 0 "l_register_operand" "") (plus:HI (match_dup 0) (const_int -1))) - (clobber (match_operand:QI 3 "d_register_operand" ""))]) + (clobber (match_operand:QI 3 "d_register_operand" "")) + (clobber (reg:CC REG_CC))]) (parallel [(set (reg:CC REG_CC) (compare:CC (match_dup 0) (const_int -1))) (clobber (match_operand:QI 1 "d_register_operand" ""))]) - (set (pc) - (if_then_else (eqne (reg:CC REG_CC) - (const_int 0)) - (label_ref (match_operand 2 "" "")) - (pc)))] + (parallel [(set (pc) + (if_then_else (eqne (reg:CC REG_CC) + (const_int 0)) + (label_ref (match_operand 2 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" { const char *op; @@ -7735,17 +7820,19 @@ (define_peephole ; "*dec-and-branchhi!=-1.l.clobber" }) (define_peephole ; "*dec-and-branchqi!=-1" - [(set (match_operand:QI 0 "d_register_operand" "") - (plus:QI (match_dup 0) - (const_int -1))) + [(parallel [(set (match_operand:QI 0 "d_register_operand" "") + (plus:QI (match_dup 0) + (const_int -1))) + (clobber (reg:CC REG_CC))]) (set (reg:CC REG_CC) (compare:CC (match_dup 0) (const_int -1))) - (set (pc) - (if_then_else (eqne (reg:CC REG_CC) - (const_int 0)) - (label_ref (match_operand 1 "" "")) - (pc)))] + (parallel [(set (pc) + (if_then_else (eqne (reg:CC REG_CC) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "" { const char *op; @@ -7773,11 +7860,12 @@ (define_peephole ; "*cpse.eq" [(set (reg:CC REG_CC) (compare:CC (match_operand:ALL1 1 "register_operand" "r,r") (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00"))) - (set (pc) - (if_then_else (eq (reg:CC REG_CC) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] + (parallel [(set (pc) + (if_then_else (eq (reg:CC REG_CC) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "jump_over_one_insn_p (insn, operands[0])" "@ cpse %1,%2 @@ -7808,11 +7896,12 @@ (define_peephole ; "*cpse.ne" [(set (reg:CC REG_CC) (compare:CC (match_operand:ALL1 1 "register_operand" "") (match_operand:ALL1 2 "reg_or_0_operand" ""))) - (set (pc) - (if_then_else (ne (reg:CC REG_CC) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] + (parallel [(set (pc) + (if_then_else (ne (reg:CC REG_CC) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:CC REG_CC))])] "!AVR_HAVE_JMP_CALL || !TARGET_SKIP_BUG" { @@ -9391,14 +9480,17 @@ (define_insn_and_split "*iorhi3.ashift8-reg.zerox" (define_peephole2 - [(set (match_operand:QI 0 "register_operand") - (const_int 0)) - (set (match_dup 0) - (ior:QI (match_dup 0) - (match_operand:QI 1 "register_operand")))] + [(parallel [(set (match_operand:QI 0 "register_operand") + (const_int 0)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (ior:QI (match_dup 0) + (match_operand:QI 1 "register_operand"))) + (clobber (reg:CC REG_CC))])] "" - [(set (match_dup 0) - (match_dup 1))]) + [(parallel [(set (match_dup 0) + (match_dup 1)) + (clobber (reg:CC REG_CC))])]) (define_expand "extzv"