Re: [PATCH][rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1

[Richard Sandiford <rdsandiford@googlemail.com>]

Sorry for the slow response.  Jeff has approved the patch in the
meantime, but I didn't want to go ahead and apply it while there
was still disagreement...

Eric Botcazou <ebotcazou@adacore.com> writes:
>> Please be more specific though.  If you don't think the patch is correct,
>> what do you think the requirement should be and how should it be integrated
>> into the existing checks?
>
> Good question, but I have asked it first. :-)
>
> So what are the new subregs that we want to accept here?  Can someone write 
> this down explicitly, I think that we cannot go ahead without that.

The idea is that if:

(1) we have a non-paradoxical subreg;
(2) both (reg:ymode xregno) and (reg:xmode xregno) occupy full
    hard registers (no padding or unused upper bits);
(3) (reg:ymode xregno) and (reg:xmode xregno) store the same number
    of bytes (X) in each constituent hard register;
(4) the offset is a multiple of X, i.e. the data we're accessing
    is aligned to a register boundary; and
(5) endianness is regular (no differences between words and bytes,
    or between registers and memory)

then the register offset is always the byte offset divided by X.

>> E.g. the assert is there because the main calculation is based on:
>> 
>>   /* Size of ymode must not be greater than the size of xmode.  */
>>   mode_multiple = GET_MODE_SIZE (xmode) / GET_MODE_SIZE (ymode);
>>   gcc_assert (mode_multiple != 0);
>> 
>> which clearly isn't a useful value if the division isn't exact.
>> Do you mean that, since mode_multiple isn't correct for the
>> DI-of-a-CI case, we should reformulate the end of the function
>> to avoid using mode_multiple at all?
>
> Yes.

It's not really obvious to me how to do that though.  Maybe I just
don't understand the cases that the existing code is trying to handle
well enough.

Thanks,
Richard