Re: [Patch] 2/3 MIPS support for builtin __builtin_flush_icache().

[Richard Sandiford <rsandifo@nildram.co.uk>]

Thanks for all the updates.  This patch looks good.

David Daney <ddaney@avtrex.com> writes:
> INITIALIZE_TRAMPOLINE now uses the new clear_cache insn.  This means 
> that it has to add the trampoline size to the ADDR argument before 
> expanding clear_cache.  If clear_cache expands to a library call, it has 
> to subtract BEGIN from END to get the length.  Looking at the generated 
> code it appears that the RTL optimizers see that this 
> addition/subtraction pair cancel each other out, and somewhat optimal 
> code is generated.

It's good to know that the sequence is optimised.  I agree this is
the way to go.  Just a few minor comments:

> +/* ISA includes synci, jr.hb and jalr.hb */

".  */"

> +  /* Load INC with the cache line size (rdhwr INC,$1). */
> +  inc = gen_reg_rtx (SImode);

Just for the record, this will eventually need to be Pmode too,
but we'd then need two rdhwr patterns.  I'll leave that to whoever
adds MIPS64r2 support though; there's no need to change the patch here.

> +  emit_insn (gen_rdhwr (inc , const1_rtx));

"inc, const1_rtx"

> +  else if (mips_cache_flush_func && mips_cache_flush_func[0])
> +    {
> +      rtx len = gen_reg_rtx (SImode);
> +      emit_insn (gen_sub3_insn (len, operands[1], operands[0]));

This too should be Pmode, since the two input operands are Pmode.
(AIUI, it's OK to pass a Pmode value to emit_library_call, even if
the argument is SImode.)  Please make this change, since it's
trivial in this context.

OK with those three changes.  They're all trivial, so if it compiles,
there's no need to retest.

Richard