From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32165 invoked by alias); 23 Apr 2014 14:05:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 32152 invoked by uid 89); 23 Apr 2014 14:05:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f50.google.com Received: from mail-wg0-f50.google.com (HELO mail-wg0-f50.google.com) (74.125.82.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 23 Apr 2014 14:05:50 +0000 Received: by mail-wg0-f50.google.com with SMTP id x13so925335wgg.9 for ; Wed, 23 Apr 2014 07:05:47 -0700 (PDT) X-Received: by 10.194.63.196 with SMTP id i4mr2548047wjs.50.1398261947019; Wed, 23 Apr 2014 07:05:47 -0700 (PDT) Received: from sandifor-thinkpad.stglab.manchester.uk.ibm.com ([2.26.169.52]) by mx.google.com with ESMTPSA id c7sm1671981wjf.19.2014.04.23.07.05.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Apr 2014 07:05:46 -0700 (PDT) From: Richard Sandiford To: Robert Suchanek Mail-Followup-To: Robert Suchanek ,"gcc-patches\@gcc.gnu.org" , "vmakarov\@redhat.com" , rdsandiford@googlemail.com Cc: "gcc-patches\@gcc.gnu.org" , "vmakarov\@redhat.com" Subject: Re: [RFC][PATCH][MIPS] Patch to enable LRA for MIPS backend References: <87d2h51dm6.fsf@talisman.default> <87d2gqfb7t.fsf@talisman.default> <87ob02jodp.fsf@talisman.default> <87fvl6hnw2.fsf@talisman.default> Date: Wed, 23 Apr 2014 14:10:00 -0000 In-Reply-To: (Robert Suchanek's message of "Wed, 23 Apr 2014 13:34:17 +0000") Message-ID: <87ioq0w37w.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2014-04/txt/msg01423.txt.bz2 Robert Suchanek writes: > If we were going to XFAIL the test then it would apply specifically > for -mips16 -O1. In any other combination it appears to work. Would > that be a stopper? Hmm, in that case maybe we should just leave it failing. The alternative would be to skip the test altogther for MIPS, with a PR referencing it, but that seems a bit over-the-top. > 2014-03-26 Robert Suchanek > > * lra-constraints.c (base_to_reg): New function. > (process_address): Use new function. > > * config/mips/constraints.md ("d"): BASE_REG_CLASS > replaced by "TARGET_MIPS16 ? M16_REGS : GR_REGS". > * config/mips/mips.c (mips_regno_mode_ok_for_base_p): > Remove use !strict_p for MIPS16. > (mips_register_priority): New function that implements > the target hook TARGET_REGISTER_PRIORITY. > (mips_spill_class): Likewise for TARGET_SPILL_CLASS > (mips_lra_p): Likewise for TARGET_LRA_P. > * config/mips/mips.h (reg_class): Add M16_SP_REGS and SPILL_REGS > classes. > (REG_CLASS_NAMES): Likewise. > (REG_CLASS_CONTENTS): Likewise. > (BASE_REG_CLASS): Use M16_SP_REGS. > * config/mips/mips.md (*mul_acc_si, *mul_sub_si): Add alternative > tuned for LRA. New set attribute to enable alternatives > depending on the register allocator used. > (*lea64): Disable pattern for MIPS16. > * config/mips/mips.opt > (mlra): New option Looks good. > @@ -12115,6 +12102,18 @@ mips_register_move_cost (enum machine_mode mode, > return 0; > } > > +/* Return a register priority for hard reg REGNO. */ > + > +static int > +mips_register_priority (int hard_regno) > +{ > + /* Treat MIPS16 registers with higher priority than other regs. */ > + if (TARGET_MIPS16 > + && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno)) > + return 1; > + return 0; > +} > + > /* Implement TARGET_MEMORY_MOVE_COST. */ > > static int > @@ -18897,6 +18896,21 @@ mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) > *update = build2 (COMPOUND_EXPR, void_type_node, *update, > atomic_feraiseexcept_call); > } > + > +static reg_class_t > +mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED, > + enum machine_mode mode ATTRIBUTE_UNUSED) > +{ > + if (TARGET_MIPS16) > + return SPILL_REGS; > + return NO_REGS; > +} > + > +static bool > +mips_lra_p (void) > +{ > + return mips_lra_flag; > +} > > /* Initialize the GCC target structure. */ > #undef TARGET_ASM_ALIGNED_HI_OP Please use comments of the form: /* Implement TARGET_FOO. */ above all three functions (instead of the current one in the case of mips_register_priority), just so that it's painfully obvious that these are target hooks. OK for the MIPS part with that change, thanks. Out of interest, do you see any difference if you include $sp in SPILL_REGS? That obviously doesn't make much conceptual sense, but it would give a cleaner class hierarchy. Richard