[AArch64][SVE] Add ABS support

[AArch64][SVE] Add ABS support

[Richard Sandiford]

For some reason we missed ABS out of the list of supported integer
operations when adding the SVE port initially.

Applied after testing on aarch64-linux-gnu and aarch64_be-elf.

Richard


2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (SVE_INT_UNARY, fp_int_op): Add abs.
	(SVE_FP_UNARY): Sort.

gcc/testsuite/
	* gcc.target/aarch64/pr64946.c: Force nosve.
	* gcc.target/aarch64/ssadv16qi.c: Likewise.
	* gcc.target/aarch64/usadv16qi.c: Likewise.
	* gcc.target/aarch64/vect-abs-compile.c: Likewise.
	* gcc.target/aarch64/sve/abs_1.c: New test.

Index: gcc/config/aarch64/iterators.md
===================================================================
--- gcc/config/aarch64/iterators.md	2018-12-11 15:49:18.249550929 +0000
+++ gcc/config/aarch64/iterators.md	2018-12-20 16:33:03.401872968 +0000
@@ -1209,10 +1209,10 @@ (define_code_iterator UCOMPARISONS [ltu
 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
 
 ;; SVE integer unary operations.
-(define_code_iterator SVE_INT_UNARY [neg not popcount])
+(define_code_iterator SVE_INT_UNARY [abs neg not popcount])
 
 ;; SVE floating-point unary operations.
-(define_code_iterator SVE_FP_UNARY [neg abs sqrt])
+(define_code_iterator SVE_FP_UNARY [abs neg sqrt])
 
 ;; SVE integer binary operations.
 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
@@ -1401,6 +1401,7 @@ (define_code_attr sve_int_op [(plus "add
 			      (mult "mul")
 			      (div "sdiv")
 			      (udiv "udiv")
+			      (abs "abs")
 			      (neg "neg")
 			      (smin "smin")
 			      (smax "smax")
Index: gcc/testsuite/gcc.target/aarch64/pr64946.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/pr64946.c	2018-06-18 15:22:36.634299637 +0100
+++ gcc/testsuite/gcc.target/aarch64/pr64946.c	2018-12-20 16:33:03.401872968 +0000
@@ -1,7 +1,8 @@
-
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 signed char a[100],b[100];
 void absolute_s8 (void)
 {
Index: gcc/testsuite/gcc.target/aarch64/ssadv16qi.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/ssadv16qi.c	2018-06-14 12:27:25.264162082 +0100
+++ gcc/testsuite/gcc.target/aarch64/ssadv16qi.c	2018-12-20 16:33:03.401872968 +0000
@@ -1,6 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 #define N 1024
 
 signed char pix1[N], pix2[N];
Index: gcc/testsuite/gcc.target/aarch64/usadv16qi.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/usadv16qi.c	2018-06-14 12:27:25.236162328 +0100
+++ gcc/testsuite/gcc.target/aarch64/usadv16qi.c	2018-12-20 16:33:03.401872968 +0000
@@ -1,6 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 #define N 1024
 
 unsigned char pix1[N], pix2[N];
Index: gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c	2018-06-18 15:22:36.638299602 +0100
+++ gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c	2018-12-20 16:33:03.401872968 +0000
@@ -1,7 +1,8 @@
-
 /* { dg-do compile } */
 /* { dg-options "-O3 -fno-vect-cost-model" } */
 
+#pragma GCC target "+nosve"
+
 #define N 16
 
 #include "vect-abs.x"
Index: gcc/testsuite/gcc.target/aarch64/sve/abs_1.c
===================================================================
--- /dev/null	2018-11-29 13:15:04.463550658 +0000
+++ gcc/testsuite/gcc.target/aarch64/sve/abs_1.c	2018-12-20 16:33:03.401872968 +0000
@@ -0,0 +1,21 @@
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <stdint.h>
+
+#define DO_OPS(TYPE)					\
+void vneg_##TYPE (TYPE *dst, TYPE *src, int count)	\
+{							\
+  for (int i = 0; i < count; ++i)			\
+    dst[i] = src[i] < 0 ? -src[i] : src[i];		\
+}
+
+DO_OPS (int8_t)
+DO_OPS (int16_t)
+DO_OPS (int32_t)
+DO_OPS (int64_t)
+
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 1 } } */