From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 63208 invoked by alias); 12 Dec 2018 18:49:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 62913 invoked by uid 89); 12 Dec 2018 18:49:30 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Dec 2018 18:49:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D8CBF80D; Wed, 12 Dec 2018 10:49:27 -0800 (PST) Received: from localhost (unknown [10.32.99.101]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3A7773F575; Wed, 12 Dec 2018 10:49:27 -0800 (PST) From: Richard Sandiford To: Steve Ellcey Mail-Followup-To: Steve Ellcey ,gcc-patches , richard.sandiford@arm.com Cc: gcc-patches Subject: Re: [EXT] Re: [Patch 1/4][Aarch64] v2: Implement Aarch64 SIMD ABI References: <1541699539.12016.6.camel@cavium.com> <87in05utpk.fsf@arm.com> <5215c53c2e14b1b1980fe4294516b2eea0053391.camel@marvell.com> <87woofas9w.fsf@arm.com> <66f33a10d020f9da9b5c931925b3bcdc9328c407.camel@marvell.com> Date: Wed, 12 Dec 2018 18:49:00 -0000 In-Reply-To: <66f33a10d020f9da9b5c931925b3bcdc9328c407.camel@marvell.com> (Steve Ellcey's message of "Wed, 12 Dec 2018 18:26:28 +0000") Message-ID: <87k1keeg22.fsf@arm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2018-12/txt/msg00858.txt.bz2 Steve Ellcey writes: > On Wed, 2018-12-12 at 11:39 +0000, Richard Sandiford wrote: >> >> Steve Ellcey writes: >> > On Fri, 2018-12-07 at 17:34 +0000, Richard Sandiford wrote: >> > > > + (match_operand:TX 2 "register_operand" "w")) >> > > > + (set (mem:TX (plus:P (match_dup 0) >> > > > + (match_operand:P 5 "const_int_operand" >> > > > "n"))) >> > > > + (match_operand:TX 3 "register_operand" "w"))])] >> > > >> > > Think this last part should be: >> > > >> > > (set (mem:TX (plus:P (plus:P (match_dup 0) >> > > (match_dup 4)) >> > > (match_operand:P 5 "const_int_operand" >> > > "n"))) >> > > (match_operand:TX 3 "register_operand" "w"))])] >> > >> > I think you are right about this. What I have for >> > loadwb_pair_ matches what is there for >> > loadwb_pair_. If this one is wrong, then I assume >> > the others are wrong too? This won't make a practical difference since >> > we call these with gen_loadwb_pair*_* calls and not via pattern >> > recognition, but still they should be right. Should I change them >> > all? I did not change this as part of this patch. >> >> I think we should fix the new pattern, but I agree fixing the others >> should be a separate patch. >> >> Patch LGTM with that change. > > I am not sure this is right. I created a patch (separate from any of > the SIMD changes) to fix the storewb_pair_ and > storewb_pair_ and when I try to build GCC with > that change, gcc aborts while building libgcc. I didn't think > this change could affect the build but it appears to do so. You're right, sorry, I'd misread the code. Patch LGTM as posted. Thanks, Richard