From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by sourceware.org (Postfix) with ESMTPS id 48DF7385DC06 for ; Wed, 27 Mar 2024 12:56:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 48DF7385DC06 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=baylibre.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 48DF7385DC06 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::329 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1711544167; cv=none; b=hDDuFf6HHpFcKh+LdjOvIfjdOma5+6EuH3uW5Tih9w4Y3mCqI6+2POMXQVT0JcfyTXl2h9sJwyz0OGsfN+CNFYzVqXI92/OKrCJ3O3hbCK+xEjBj7AVjjJcv1TxwbTLdOk3DWZx0OrOFnpCavYS6CEcBSGhEO2ei0cjiQNEHi+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1711544167; c=relaxed/simple; bh=vFXvQxHcSr8XYSGa32lba6qNHjR8cXHPwKOTRo4d8DI=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=pBkZuXuls72P5AefzeRj/BSimV68XQzdkOQdX9SPrAT+nVnXtGJ6UpotGexKGgMOoRINg12VtRHPQe+caFnNncR00rgMAMX0VpZ+smbc8YfaAOUTYbxs+h1pJR+iF0cfO6P7RtjQc2aukHKoZTsF0BDw9Wasx++spxQMCyqJpas= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-41495430387so4276005e9.0 for ; Wed, 27 Mar 2024 05:56:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1711544163; x=1712148963; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:user-agent :references:in-reply-to:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5CRe9He2RbNpRe5XpudZiLOVXB6cPBL2CeeDX2GOGLA=; b=lV3RHGZ/2ZzjeaHmZ2yAY7k9IYExKzIF9tfBoz5vICerYz4viWW1j3lUAm5sER4IA7 vIZH8f4H7/qD9SCng3VZ78Cg3Lox5qi/4mn/sAHGbzDqyNhldz+8iTUiRogTXt/Jh5fP vuJ7gGo1WLuSXfmafxF5AYgS6/o2USv2zRj2WCOfs90dUp2yXNwb2t4wkYAcIVrVZYcF t4xm76+Hk63wFqUdDMfYpq5aiNCpQl8g60szHr9sfcGcPaeCNQo0pLJT+5LjggGPoFNL I16SZksGvGjvg/VEqwinVN0ex7PFdUPHNTlpwOx/LPk8ndLBCTSSHTawmIXlPVOJGXWZ ta3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711544163; x=1712148963; h=content-transfer-encoding:mime-version:message-id:date:user-agent :references:in-reply-to:subject:cc:to:from:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5CRe9He2RbNpRe5XpudZiLOVXB6cPBL2CeeDX2GOGLA=; b=rze4mml8cie4IUpgae1JS0EI6fl/+HfXgAjMAGKyjJl47FZvPpfyiguBD8Unyty6ZO RiWp0agLAyckja7xbvYVhPAes5mJN8zl2ikicOvigAqzuKWWNfme0bDeBSl3mMDTY99X vYv/o76MJfa2+85h1yqLYsJfBKxkovhVVgnpscrPW6eJ70+ZGiEbbbsDycJkYzEEbIUd RYg8wwlQiMxKg1E2djkVzSBjfSY8MBPs6D8ZUViuwWGFko+eOq/qKu6/RBm5/Z491AJA YYDrIIm2FG8fFj5hUcs4Exfxxum9nsCcEP5FSaUmT/j8I/L80CW4CFWg7N5kZ/Qzyk2e EDzg== X-Forwarded-Encrypted: i=1; AJvYcCXHixeddISFwb73TC/IhEtrDFgrXhw6MeMZ4xeEIg4iZke4zgV0/+0uPLPNQ1jy1kwxd9Owl3YPqL4sghYv++Vaycljy2jVrg== X-Gm-Message-State: AOJu0YwyBhlG9lSlU461BN0XjzuSaA8DWVjeeu0wj59Mvq7z2dgcwcNf Tk+ASYLABkt8nDHBCBYaK2pvHLkcgJ3Frnkx3rPZmndUXfEU2BuPmR7epWoql5s= X-Google-Smtp-Source: AGHT+IEft1q7xVNjD4S+NBFC+lye+996kp0egIOasncHxhERF+EyPzYO+QdTYgiYE6nrIS8Njx1HAQ== X-Received: by 2002:a05:600c:4f06:b0:414:24d:7f9 with SMTP id l6-20020a05600c4f0600b00414024d07f9mr2642229wmq.1.1711544162975; Wed, 27 Mar 2024 05:56:02 -0700 (PDT) Received: from dem-tschwing-1.ger.mentorg.com (laubervilliers-657-1-248-155.w90-24.abo.wanadoo.fr. [90.24.137.155]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b004146a1bf590sm2055934wmb.32.2024.03.27.05.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 05:56:02 -0700 (PDT) From: Thomas Schwinge To: Andrew Stubbs Cc: Richard Biener , gcc-patches@gcc.gnu.org Subject: Re: [PATCH] vect: more oversized bitmask fixups In-Reply-To: References: <20240321142225.52854-1-ams@baylibre.com> <8b4049ae-bf20-4130-80e7-c07eb3668942@baylibre.com> User-Agent: Notmuch/0.30+7~gb1d4d05 (https://notmuchmail.org) Emacs/27.1 (x86_64-pc-linux-gnu) Date: Wed, 27 Mar 2024 13:56:01 +0100 Message-ID: <87le63al5q.fsf@dem-tschwing-1.schwinge.ddns.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi! On 2024-03-22T14:15:36+0000, Andrew Stubbs wrote: > On 22/03/2024 08:43, Richard Biener wrote: > Thanks, here's what I pushed. > vect: more oversized bitmask fixups > > These patches fix up a failure in testcase vect/tsvc/vect-tsvc-s278.c when > configured to use V32 instead of V64 (I plan to do this for RDNA devices). Thanks, confirming that this "vect: more oversized bitmask fixups" does fix the GCN target '-march=3Dgfx1100' testing regression: PASS: gcc.dg/vect/tsvc/vect-tsvc-s278.c (test for excess errors) [-PASS:-]{+FAIL:+} gcc.dg/vect/tsvc/vect-tsvc-s278.c execution test XPASS: gcc.dg/vect/tsvc/vect-tsvc-s278.c scan-tree-dump vect "vectorize= d 1 loops" PASS: gcc.dg/vect/tsvc/vect-tsvc-s279.c (test for excess errors) [-PASS:-]{+FAIL:+} gcc.dg/vect/tsvc/vect-tsvc-s279.c execution test XPASS: gcc.dg/vect/tsvc/vect-tsvc-s279.c scan-tree-dump vect "vectorize= d 1 loops" ... that I saw introduced by "amdgcn: Prefer V32 on RDNA devices". (The XPASSes are independent of that, pre-existing.) Gr=C3=BC=C3=9Fe Thomas > The problem was that a "not" operation on the mask inadvertently enabled > inactive lanes 31-63 and corrupted the output. The fix is to adjust the = mask > when calling internal functions (in this case COND_MINUS), when doing mas= ked > loads and stores, and when doing conditional jumps (some cases were alrea= dy > handled). > > gcc/ChangeLog: > > * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector > bitmasks. > (do_compare_and_jump): Remove now-redundant similar code. > * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector > bitmasks. > (add_mask_and_len_args): Likewise. > > diff --git a/gcc/dojump.cc b/gcc/dojump.cc > index 88600cb42d3..5f74b696b41 100644 > --- a/gcc/dojump.cc > +++ b/gcc/dojump.cc > @@ -1235,6 +1235,24 @@ do_compare_rtx_and_jump (rtx op0, rtx op1, enum rt= x_code code, int unsignedp, > } > } >=20=20 > + /* For boolean vectors with less than mode precision > + make sure to fill padding with consistent values. */ > + if (val > + && VECTOR_BOOLEAN_TYPE_P (TREE_TYPE (val)) > + && SCALAR_INT_MODE_P (mode)) > + { > + auto nunits =3D TYPE_VECTOR_SUBPARTS (TREE_TYPE (val)).to_constant (); > + if (maybe_ne (GET_MODE_PRECISION (mode), nunits)) > + { > + op0 =3D expand_binop (mode, and_optab, op0, > + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), > + NULL_RTX, true, OPTAB_WIDEN); > + op1 =3D expand_binop (mode, and_optab, op1, > + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), > + NULL_RTX, true, OPTAB_WIDEN); > + } > + } > + > emit_cmp_and_jump_insns (op0, op1, code, size, mode, unsignedp, va= l, > if_true_label, prob); > } > @@ -1266,7 +1284,6 @@ do_compare_and_jump (tree treeop0, tree treeop1, en= um rtx_code signed_code, > machine_mode mode; > int unsignedp; > enum rtx_code code; > - unsigned HOST_WIDE_INT nunits; >=20=20 > /* Don't crash if the comparison was erroneous. */ > op0 =3D expand_normal (treeop0); > @@ -1309,21 +1326,6 @@ do_compare_and_jump (tree treeop0, tree treeop1, e= num rtx_code signed_code, > emit_insn (targetm.gen_canonicalize_funcptr_for_compare (new_op1, = op1)); > op1 =3D new_op1; > } > - /* For boolean vectors with less than mode precision > - make sure to fill padding with consistent values. */ > - else if (VECTOR_BOOLEAN_TYPE_P (type) > - && SCALAR_INT_MODE_P (mode) > - && TYPE_VECTOR_SUBPARTS (type).is_constant (&nunits) > - && maybe_ne (GET_MODE_PRECISION (mode), nunits)) > - { > - gcc_assert (code =3D=3D EQ || code =3D=3D NE); > - op0 =3D expand_binop (mode, and_optab, op0, > - GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), NULL_RTX, > - true, OPTAB_WIDEN); > - op1 =3D expand_binop (mode, and_optab, op1, > - GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), NULL_RTX, > - true, OPTAB_WIDEN); > - } >=20=20 > do_compare_rtx_and_jump (op0, op1, code, unsignedp, treeop0, mode, > ((mode =3D=3D BLKmode) > diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc > index fcf47c7fa12..5269f0ac528 100644 > --- a/gcc/internal-fn.cc > +++ b/gcc/internal-fn.cc > @@ -245,6 +245,18 @@ expand_fn_using_insn (gcall *stmt, insn_code icode, = unsigned int noutputs, > && SSA_NAME_IS_DEFAULT_DEF (rhs) > && VAR_P (SSA_NAME_VAR (rhs))) > create_undefined_input_operand (&ops[opno], TYPE_MODE (rhs_type)); > + else if (VECTOR_BOOLEAN_TYPE_P (rhs_type) > + && SCALAR_INT_MODE_P (TYPE_MODE (rhs_type)) > + && maybe_ne (GET_MODE_PRECISION (TYPE_MODE (rhs_type)), > + TYPE_VECTOR_SUBPARTS (rhs_type).to_constant ())) > + { > + /* Ensure that the vector bitmasks do not have excess bits. */ > + int nunits =3D TYPE_VECTOR_SUBPARTS (rhs_type).to_constant (); > + rtx tmp =3D expand_binop (TYPE_MODE (rhs_type), and_optab, rhs_rtx, > + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), > + NULL_RTX, true, OPTAB_WIDEN); > + create_input_operand (&ops[opno], tmp, TYPE_MODE (rhs_type)); > + } > else > create_input_operand (&ops[opno], rhs_rtx, TYPE_MODE (rhs_type)); > opno +=3D 1; > @@ -312,6 +324,20 @@ add_mask_and_len_args (expand_operand *ops, unsigned= int opno, gcall *stmt) > { > tree mask =3D gimple_call_arg (stmt, mask_index); > rtx mask_rtx =3D expand_normal (mask); > + > + tree mask_type =3D TREE_TYPE (mask); > + if (VECTOR_BOOLEAN_TYPE_P (mask_type) > + && SCALAR_INT_MODE_P (TYPE_MODE (mask_type)) > + && maybe_ne (GET_MODE_PRECISION (TYPE_MODE (mask_type)), > + TYPE_VECTOR_SUBPARTS (mask_type).to_constant ())) > + { > + /* Ensure that the vector bitmasks do not have excess bits. */ > + int nunits =3D TYPE_VECTOR_SUBPARTS (mask_type).to_constant (); > + mask_rtx =3D expand_binop (TYPE_MODE (mask_type), and_optab, mask_rtx, > + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), > + NULL_RTX, true, OPTAB_WIDEN); > + } > + > create_input_operand (&ops[opno++], mask_rtx, > TYPE_MODE (TREE_TYPE (mask))); > }