From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27018 invoked by alias); 8 Jan 2013 07:22:49 -0000 Received: (qmail 27009 invoked by uid 22791); 8 Jan 2013 07:22:48 -0000 X-SWARE-Spam-Status: No, hits=-3.6 required=5.0 tests=AWL,BAYES_00,DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,KHOP_RCVD_TRUST,NML_ADSP_CUSTOM_MED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-we0-f179.google.com (HELO mail-we0-f179.google.com) (74.125.82.179) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 08 Jan 2013 07:22:42 +0000 Received: by mail-we0-f179.google.com with SMTP id r6so61389wey.38 for ; Mon, 07 Jan 2013 23:22:41 -0800 (PST) X-Received: by 10.194.57.206 with SMTP id k14mr99435851wjq.26.1357629761137; Mon, 07 Jan 2013 23:22:41 -0800 (PST) Received: from localhost ([2.26.203.77]) by mx.google.com with ESMTPS id hg17sm15328261wib.1.2013.01.07.23.22.39 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 07 Jan 2013 23:22:40 -0800 (PST) From: Richard Sandiford To: Jeff Law Mail-Followup-To: Jeff Law , =?utf-8?Q?J=C3=BCrgen?= Urban , gcc-patches@gcc.gnu.org, rdsandiford@googlemail.com Cc: =?utf-8?Q?J=C3=BCrgen?= Urban , gcc-patches@gcc.gnu.org Subject: Re: Support for MIPS r5900 References: <20130106225645.190700@gmx.net> <87y5g43bkf.fsf@talisman.default> <50EB9EF4.9090804@redhat.com> Date: Tue, 08 Jan 2013 07:22:00 -0000 In-Reply-To: <50EB9EF4.9090804@redhat.com> (Jeff Law's message of "Mon, 07 Jan 2013 21:22:12 -0700") Message-ID: <87mwwk2l6p.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2013-01/txt/msg00385.txt.bz2 Jeff Law writes: > On 01/07/2013 02:52 PM, Richard Sandiford wrote: > >>> I disabled 64 bit FPU instructions by "-msoft-float". This works, but >>> using "-msingle-float" fails. This would be the better >>> configuration. There are still 64 bit FPU instructions used (e.g. "dmfc1 >>> $2,$f0" when using "long double" multiplication). So "-msingle-float" >>> doesn't seem to work on generic mips64-linux-gnu. >> >> Right. That combination hasn't really been defined. What happens >> for plain doubles? Do you pass those in FPRs or GPRs? > IIRC we defined doubles as 32bits wide in our old port. We simply=20 > didn't support 64bit wide doubles. I don't remember what mechanism we=20 > used to make this happen. Ah, yeah. >>> I tried to disable dmult and ddiv (see mips.md). Disabling worked, but >>> now muldi3 calls itself in libgcc2. I thought this should work, because >>> I got this working with GCC 4.3, but the latest GCC version is a >>> problem. multi3 is calling muldi3, so that muldi3 should be able to use >>> mulsi3, because it is the same C code in libgcc2. Can someone get me >>> some hints or comments? How can this be debugged? >> >> Not sure, sorry. > IIRC I simply disabled muldi3_internal2 and I think we defined away=20 > everything related to timode except register-register moves. AIUI the problem that J=C3=BCrgen's hitting is that _muldi3.o in libgcc actually contains __multi3 on 64-bit targets, because LIBGCC2_UNITS_PER_WORD =3D=3D 8. Presumably _mulsi3.o would then contain __muldi3 where needed, but that file doesn't exist. So he was trying to add it. If this worked in 4.3 then I assume something has changed in the last few years. Richard