From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9270 invoked by alias); 25 Jul 2007 18:14:33 -0000 Received: (qmail 9260 invoked by uid 22791); 25 Jul 2007 18:14:32 -0000 X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (65.74.133.4) by sourceware.org (qpsmtpd/0.31) with ESMTP; Wed, 25 Jul 2007 18:14:30 +0000 Received: (qmail 30993 invoked from network); 25 Jul 2007 18:14:29 -0000 Received: from unknown (HELO gateway) (10.0.0.100) by mail.codesourcery.com with SMTP; 25 Jul 2007 18:14:29 -0000 Received: by gateway (Postfix, from userid 1010) id CB5F26BDFC; Wed, 25 Jul 2007 11:14:28 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard@codesourcery.com Subject: [committed] Fix loop optimiser segfaults for MIPS16 Date: Wed, 25 Jul 2007 18:38:00 -0000 Message-ID: <87odi0e4fv.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/21.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2007-07/txt/msg01840.txt.bz2 This patch fixes several 64-bit MIPS16 testsuite failures. The tree-level loop optimisers (quite reasonably) use the backend addressing code to estimate the cost of an operation, and in some cases, this would cause us to need the MIPS16 GP pseudo register. We currently insert the initialisation of that register at the same time as we create the register, but in this case, that's too early: we don't have an instruction stream yet. The patch therefore postpones the initialisation until we're called from expand. (The check is similar to the handling of the ARM PIC register.) We don't reset reg_rtx_no before expand, so it's currently OK -- and more efficient -- to use the same pseudo register both before and during expand. The patch would have to be changed if reg_rtx_no is ever reset between times. Tested on mipsisa64-elfoabi with a version of Adam's no_new_pseudos workaround applied. Committed to trunk. Richard gcc/ * config/mips/mips.c (machine_function): Add initialized_mips16_gp_pseudo_p. (mips16_gp_pseudo_reg): Do not emit the initialization of mips16_gp_pseudo_rtx when being called from the gimple cost- calculation routines; emit it on the first use outside those routines. Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c 2007-06-27 19:56:12.000000000 -0700 +++ gcc/config/mips/mips.c 2007-06-27 20:05:57.000000000 -0700 @@ -476,6 +476,10 @@ struct machine_function GTY(()) { /* True if the function is known to have an instruction that needs $gp. */ bool has_gp_insn_p; + + /* True if we have emitted an instruction to initialize + mips16_gp_pseudo_rtx. */ + bool initialized_mips16_gp_pseudo_p; }; /* Information about a single argument. */ @@ -8616,11 +8619,15 @@ mips_vector_mode_supported_p (enum machi mips16_gp_pseudo_reg (void) { if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX) + cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); + + /* Don't initialize the pseudo register if we are being called from + the tree optimizers' cost-calculation routines. */ + if (!cfun->machine->initialized_mips16_gp_pseudo_p + && current_ir_type () != IR_GIMPLE) { rtx insn, scan; - cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); - /* We want to initialize this to a value which gcc will believe is constant. */ insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); @@ -8636,6 +8643,8 @@ mips16_gp_pseudo_reg (void) scan = get_insns (); insn = emit_insn_after (insn, scan); pop_topmost_sequence (); + + cfun->machine->initialized_mips16_gp_pseudo_p = true; } return cfun->machine->mips16_gp_pseudo_rtx;