From: Andreas Schwab <schwab@linux-m68k.org>
To: "Li, Pan2" <pan2.li@intel.com>
Cc: Kito Cheng <kito.cheng@gmail.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
"juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
"Wang, Yanzhang" <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Allow RVV intrinsic when function target("arch=+v")
Date: Fri, 29 Mar 2024 21:24:52 +0100 [thread overview]
Message-ID: <87r0fspyzv.fsf@igel.home> (raw)
In-Reply-To: <MW5PR11MB5908235AE8DDE229648830F7A9362@MW5PR11MB5908.namprd11.prod.outlook.com> (Pan2 Li's message of "Mon, 25 Mar 2024 12:13:58 +0000")
../../gcc/config/riscv/riscv-vector-builtins.cc: In function 'rtx_def* riscv_vector::expand_builtin(unsigned int, tree, rtx)':
../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error: misspelled term 'builtin function' in format; use 'built-in function' instead [-Werror=format-diag]
4592 | "builtin function %qE requires the V ISA extension", exp);
| ^~~~~~~~~~~~~~~~
cc1plus: all warnings being treated as errors
make[3]: *** [../../gcc/config/riscv/t-riscv:28: riscv-vector-builtins.o] Error 1
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
prev parent reply other threads:[~2024-03-29 20:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-25 7:42 pan2.li
2024-03-25 12:04 ` Kito Cheng
2024-03-25 12:13 ` Li, Pan2
2024-03-29 20:24 ` Andreas Schwab [this message]
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