From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22788 invoked by alias); 24 Jun 2014 20:19:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 22778 invoked by uid 89); 24 Jun 2014 20:19:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f171.google.com Received: from mail-wi0-f171.google.com (HELO mail-wi0-f171.google.com) (209.85.212.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 24 Jun 2014 20:19:35 +0000 Received: by mail-wi0-f171.google.com with SMTP id n15so6687537wiw.16 for ; Tue, 24 Jun 2014 13:19:28 -0700 (PDT) X-Received: by 10.180.83.225 with SMTP id t1mr5261450wiy.28.1403641168100; Tue, 24 Jun 2014 13:19:28 -0700 (PDT) Received: from localhost ([2.26.169.52]) by mx.google.com with ESMTPSA id i6sm4791156wiy.17.2014.06.24.13.19.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jun 2014 13:19:27 -0700 (PDT) From: Richard Sandiford To: Sandra Loosemore Mail-Followup-To: Sandra Loosemore ,Jeff Law , GCC Patches , rdsandiford@googlemail.com Cc: Jeff Law , GCC Patches Subject: Re: [patch, mips] delete bit-rotten ADJUST_REG_ALLOC_ORDER definition References: <53727C74.2070502@codesourcery.com> <5373AF23.7000206@redhat.com> <878uq4ci0m.fsf@talisman.default> <53A76C75.9090907@codesourcery.com> Date: Tue, 24 Jun 2014 20:19:00 -0000 In-Reply-To: <53A76C75.9090907@codesourcery.com> (Sandra Loosemore's message of "Sun, 22 Jun 2014 17:53:25 -0600") Message-ID: <87tx7agiwh.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2014-06/txt/msg01936.txt.bz2 Sandra Loosemore writes: > On 05/14/2014 12:49 PM, Richard Sandiford wrote: >> Jeff Law writes: >>> On 05/13/14 14:11, Sandra Loosemore wrote: >>>> >>>> 2014-05-13 Catherine Moore >>>> Sandra Loosemore >>>> >>>> gcc/ >>>> * config/mips/mips.c (mips_order_regs_for_local_alloc): Delete. >>>> * config/mips/mips.h (ADJUST_REG_ALLOC_ORDER): Delete. >>>> * config/mips/mips-protos.h (mips_order_regs_for_local_alloc): Delete. >>> OK for the trunk. >> >> Would it be OK to hold off until after the switch to LRA? That patch >> has been written and the MIPS parts approved, but we're waiting for >> some legal things to be sorted out and for a fixed version of the LRA >> EXTRA_MEMORY_CONSTRAINT patch. I just think it'd be better to tune this >> sort of thing once that's done, rather than tune it against reload. > > Richard, is it OK to commit this patch now that LRA is in, or do you > want to experiment some more with tuning first? I think we're all in > agreement that this is broken old code that should be removed regardless > of whether we do other things to tune REG_ALLOC_ORDER. Sure, go ahead. I retried with trunk and removing the definition had very little effect on non-MIPS16 and an overall positive effect on MIPS16. Which is a bit ironic, given that the hook was supposed to help MIPS16 and at face value would hurt non-MIPS16 more. It looks like moving $24 first really isn't a win for MIPS16 with IRA. To reinforce that, I tried the old patch I posted in place of yours, but moving $24 ahead of the other registers was better for non-MIPS16 code and worse for MIPS16. The MIPS16 results were as close to trunk as the non-MIPS16 ones were with your patch; just two differences. So the MIPS16 benefit of your patch really is coming from having $24 after the MIPS16 registers. The reason for the improvement in non-MIPS16 results with my patch seemed to be that putting the return and argument registers first leads to less freedom of movement and thus more unfilled delay slots. In some cases I think these were more due to reorg.c's infamous approach to register liveness rather than real interference. E.g. branches to a return statement were not having their delay slots filled with an assignment to $2 even though the return statement set $2 itself. Change the assigned register from $2 to $24 and the delay slot could be filled. So it might be interesting to experiment with putting the later call-clobbered registers first, but that's a separate change. Richard