Re: [Patch 1/4][Aarch64] v2: Implement Aarch64 SIMD ABI

[Richard Sandiford <richard.sandiford@arm.com>]

Steve Ellcey <sellcey@marvell.com> writes:
> On Fri, 2018-12-07 at 17:34 +0000, Richard Sandiford wrote:
>> > +          (match_operand:TX 2 "register_operand" "w"))
>> > +     (set (mem:TX (plus:P (match_dup 0)
>> > +                  (match_operand:P 5 "const_int_operand" "n")))
>> > +          (match_operand:TX 3 "register_operand" "w"))])]
>> 
>> Think this last part should be:
>> 
>>      (set (mem:TX (plus:P (plus:P (match_dup 0)
>>                                   (match_dup 4))
>>                           (match_operand:P 5 "const_int_operand"
>> "n")))
>>           (match_operand:TX 3 "register_operand" "w"))])]
>
> I think you are right about this.  What I have for
> loadwb_pair<TX:mode>_<P:mode> matches what is there for
> loadwb_pair<GPF:mode>_<P:mode>.  If this one is wrong, then I assume
> the others are wrong too?  This won't make a practical difference since
> we call these with gen_loadwb_pair*_* calls and not via pattern
> recognition, but still they should be right.  Should I change them
> all?  I did not change this as part of this patch.

I think we should fix the new pattern, but I agree fixing the others
should be a separate patch.

Patch LGTM with that change.

Thanks,
Richard