From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 81796 invoked by alias); 18 May 2015 18:23:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 81782 invoked by uid 89); 18 May 2015 18:23:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.0 required=5.0 tests=AWL,BAYES_50,KAM_ASCII_DIVIDERS,SPF_PASS autolearn=no version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 May 2015 18:23:17 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-3.uk.mimecast.lan; Mon, 18 May 2015 19:23:09 +0100 Received: from localhost ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 18 May 2015 19:23:09 +0100 From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [6/9] Pass REG changes through a new function References: <87oalhu59s.fsf@e105548-lin.cambridge.arm.com> Date: Mon, 18 May 2015 18:24:00 -0000 In-Reply-To: <87oalhu59s.fsf@e105548-lin.cambridge.arm.com> (Richard Sandiford's message of "Mon, 18 May 2015 19:09:19 +0100") Message-ID: <87wq05sq2a.fsf@e105548-lin.cambridge.arm.com> User-Agent: Gnus/5.130012 (Ma Gnus v0.12) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 X-MC-Unique: p39nElFDSpSptmXqY_pVuw-1 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2015-05/txt/msg01605.txt.bz2 This patch adds a new function to set both the mode and regno of a REG. It makes sure that all REG PUT_MODE and SET_REGNO changes go through this function. There's a new PUT_MODE_RAW (analogous to SET_REGNO_RAW) for the cases where the caller doesn't want that. There's a small consistency fix: gen_rtx_REG was declared with "unsigned" and defined with "unsigned int". The latter is usual GCC style. gcc/ * rtl.h (PUT_MODE_RAW): New macro. (PUT_REG_NOTE_KIND): Use it. (set_mode_and_regno): Declare. (gen_raw_REG): Change regno to "unsigned int". (gen_rtx_REG): Change "unsigned" to "unsigned int". (PUT_MODE): Forward to PUT_MODE_RAW for generators, otherwise use set_mode_and_regno to change the mode of registers. * gengenrtl.c (gendef): Use PUT_MODE_RAW. * emit-rtl.c (set_mode_and_regno): New function. (gen_raw_REG): Change regno to unsigned int. Use set_mode_and_regno. * caller-save.c (reg_save_code): Use set_mode_and_regno. * expr.c (init_expr_target): Likewise. * ira.c (setup_prohibited_mode_move_regs): Likewise. * postreload.c (reload_cse_simplify_operands): Likewise. Index: gcc/rtl.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- gcc/rtl.h 2015-05-17 21:26:44.375213705 +0100 +++ gcc/rtl.h 2015-05-17 21:29:52.068986873 +0100 @@ -668,8 +668,8 @@ #define RTX_PREV(X) ((INSN_P (X) #define GET_CODE(RTX) ((enum rtx_code) (RTX)->code) #define PUT_CODE(RTX, CODE) ((RTX)->code =3D (CODE)) =20 -#define GET_MODE(RTX) ((machine_mode) (RTX)->mode) -#define PUT_MODE(RTX, MODE) ((RTX)->mode =3D (MODE)) +#define GET_MODE(RTX) ((machine_mode) (RTX)->mode) +#define PUT_MODE_RAW(RTX, MODE) ((RTX)->mode =3D (MODE)) =20 /* RTL vector. These appear inside RTX's when there is a need for a variable number of things. The principle use is inside @@ -1509,7 +1509,7 @@ #define DEF_REG_NOTE(NAME) NAME, /* Define macros to extract and insert the reg-note kind in an EXPR_LIST. = */ #define REG_NOTE_KIND(LINK) ((enum reg_note) GET_MODE (LINK)) #define PUT_REG_NOTE_KIND(LINK, KIND) \ - PUT_MODE (LINK, (machine_mode) (KIND)) + PUT_MODE_RAW (LINK, (machine_mode) (KIND)) =20 /* Names for REG_NOTE's in EXPR_LIST insn's. */ =20 @@ -3216,13 +3216,27 @@ gen_rtx_INSN (machine_mode mode, rtx_ins rtx reg_notes); extern rtx gen_rtx_CONST_INT (machine_mode, HOST_WIDE_INT); extern rtx gen_rtx_CONST_VECTOR (machine_mode, rtvec); -extern rtx gen_raw_REG (machine_mode, int); -extern rtx gen_rtx_REG (machine_mode, unsigned); +extern void set_mode_and_regno (rtx, machine_mode, unsigned int); +extern rtx gen_raw_REG (machine_mode, unsigned int); +extern rtx gen_rtx_REG (machine_mode, unsigned int); extern rtx gen_rtx_SUBREG (machine_mode, rtx, int); extern rtx gen_rtx_MEM (machine_mode, rtx); extern rtx gen_rtx_VAR_LOCATION (machine_mode, tree, rtx, enum var_init_status); =20 +#ifdef GENERATOR_FILE +#define PUT_MODE(RTX, MODE) PUT_MODE_RAW (RTX, MODE) +#else +static inline void +PUT_MODE (rtx x, machine_mode mode) +{ + if (REG_P (x)) + set_mode_and_regno (x, mode, REGNO (x)); + else + PUT_MODE_RAW (x, mode); +} +#endif + #define GEN_INT(N) gen_rtx_CONST_INT (VOIDmode, (N)) =20 /* Virtual registers are used during RTL generation to refer to locations = into Index: gcc/gengenrtl.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- gcc/gengenrtl.c 2015-05-15 21:12:56.172234508 +0100 +++ gcc/gengenrtl.c 2015-05-17 21:31:16.143988041 +0100 @@ -252,7 +252,7 @@ gendef (const char *format) puts (" rtx rt;"); puts (" rt =3D rtx_alloc_stat (code PASS_MEM_STAT);\n"); =20 - puts (" PUT_MODE (rt, mode);"); + puts (" PUT_MODE_RAW (rt, mode);"); =20 for (p =3D format, i =3D j =3D 0; *p ; ++p, ++i) if (*p !=3D '0') Index: gcc/emit-rtl.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- gcc/emit-rtl.c 2015-05-17 21:26:44.375213705 +0100 +++ gcc/emit-rtl.c 2015-05-17 21:30:18.484672892 +0100 @@ -430,16 +430,24 @@ gen_blockage (void) #endif =20 =20 +/* Set the mode and register number of X to MODE and REGNO. */ + +void +set_mode_and_regno (rtx x, machine_mode mode, unsigned int regno) +{ + PUT_MODE_RAW (x, mode); + SET_REGNO_RAW (x, regno); +} + /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and don't attempt to share with the various global pieces of rtl (such as frame_pointer_rtx). */ =20 rtx -gen_raw_REG (machine_mode mode, int regno) +gen_raw_REG (machine_mode mode, unsigned int regno) { rtx x =3D rtx_alloc_stat (REG PASS_MEM_STAT); - PUT_MODE (x, mode); - SET_REGNO_RAW (x, regno); + set_mode_and_regno (x, mode, regno); REG_ATTRS (x) =3D NULL; ORIGINAL_REGNO (x) =3D regno; return x; Index: gcc/caller-save.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- gcc/caller-save.c 2015-05-17 21:26:44.375213705 +0100 +++ gcc/caller-save.c 2015-05-17 21:26:44.363212664 +0100 @@ -150,8 +150,7 @@ reg_save_code (int reg, machine_mode mod =20 /* Update the register number and modes of the register and memory operand. */ - SET_REGNO_RAW (test_reg, reg); - PUT_MODE (test_reg, mode); + set_mode_and_regno (test_reg, mode, reg); PUT_MODE (test_mem, mode); =20 /* Force re-recognition of the modified insns. */ Index: gcc/expr.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- gcc/expr.c 2015-05-17 21:26:44.375213705 +0100 +++ gcc/expr.c 2015-05-17 21:26:44.371213229 +0100 @@ -221,7 +221,6 @@ init_expr_target (void) direct_load[(int) mode] =3D direct_store[(int) mode] =3D 0; PUT_MODE (mem, mode); PUT_MODE (mem1, mode); - PUT_MODE (reg, mode); =20 /* See if there is some register that can be used in this mode and directly loaded or stored from memory. */ @@ -234,7 +233,7 @@ init_expr_target (void) if (! HARD_REGNO_MODE_OK (regno, mode)) continue; =20 - SET_REGNO (reg, regno); + set_mode_and_regno (reg, mode, regno); =20 SET_SRC (pat) =3D mem; SET_DEST (pat) =3D reg; Index: gcc/ira.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- gcc/ira.c 2015-05-17 21:26:44.375213705 +0100 +++ gcc/ira.c 2015-05-17 21:26:44.363212664 +0100 @@ -1778,10 +1778,8 @@ setup_prohibited_mode_move_regs (void) { if (! HARD_REGNO_MODE_OK (j, (machine_mode) i)) continue; - SET_REGNO_RAW (test_reg1, j); - PUT_MODE (test_reg1, (machine_mode) i); - SET_REGNO_RAW (test_reg2, j); - PUT_MODE (test_reg2, (machine_mode) i); + set_mode_and_regno (test_reg1, (machine_mode) i, j); + set_mode_and_regno (test_reg2, (machine_mode) i, j); INSN_CODE (move_insn) =3D -1; recog_memoized (move_insn); if (INSN_CODE (move_insn) < 0) Index: gcc/postreload.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- gcc/postreload.c 2015-05-17 21:26:44.375213705 +0100 +++ gcc/postreload.c 2015-05-17 21:26:44.367212817 +0100 @@ -562,8 +562,7 @@ reload_cse_simplify_operands (rtx_insn * if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) continue; =20 - SET_REGNO_RAW (testreg, regno); - PUT_MODE (testreg, mode); + set_mode_and_regno (testreg, mode, regno); =20 /* We found a register equal to this operand. Now look for all alternatives that can accept this register and have not been