From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26687 invoked by alias); 11 Apr 2012 19:16:16 -0000 Received: (qmail 26678 invoked by uid 22791); 11 Apr 2012 19:16:15 -0000 X-SWARE-Spam-Status: No, hits=-4.1 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,KHOP_RCVD_TRUST,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-wg0-f51.google.com (HELO mail-wg0-f51.google.com) (74.125.82.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 11 Apr 2012 19:15:46 +0000 Received: by wgbed3 with SMTP id ed3so1013123wgb.8 for ; Wed, 11 Apr 2012 12:15:45 -0700 (PDT) Received: by 10.180.82.136 with SMTP id i8mr18687693wiy.19.1334171745574; Wed, 11 Apr 2012 12:15:45 -0700 (PDT) Received: from localhost (rsandifo.gotadsl.co.uk. [82.133.89.107]) by mx.google.com with ESMTPS id fn2sm12669568wib.0.2012.04.11.12.15.44 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Apr 2012 12:15:44 -0700 (PDT) From: Richard Sandiford To: Bernd Schmidt Mail-Followup-To: Bernd Schmidt ,Peter Bigot , GCC Patches , rdsandiford@googlemail.com Cc: Peter Bigot , GCC Patches Subject: Re: Setting precision for a PSImode type References: <4F54EBFD.4060605@codesourcery.com> <4F85B775.1060905@codesourcery.com> <4F85C8FC.5060902@codesourcery.com> Date: Wed, 11 Apr 2012 19:16:00 -0000 In-Reply-To: <4F85C8FC.5060902@codesourcery.com> (Bernd Schmidt's message of "Wed, 11 Apr 2012 20:10:04 +0200") Message-ID: <87y5q2axls.fsf@talisman.home> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-04/txt/msg00692.txt.bz2 Bernd Schmidt writes: > On 04/11/2012 07:31 PM, Peter Bigot wrote: >> The biggest one is that widening from 20-bit to 32-bit is an extremely >> expensive operation: it was a 16-bit ISA, but some newer MCUs support >> an extension with 20 bits in each register and a set of new >> instructions that must be used to preserve the upper 4 bits. Getting >> bits 19..16 of a 20-bit register down into the low bits of a 16 bit >> register requires a five-position rotate-through-carry. The 20-bit >> enhancement to the ISA was really intended only to support a larger >> address space; to simplify validation of the machine description I've >> chosen to allow it to be used for any integer operation, but I have no >> reason to think that'll be common. > > Ok. So these are pointer modes, essentially? For the target I'm working > on, I'm using the following patch, see if that helps you any. It seems > to apply to trunk, so I might as well ask for an OK if it bootstraps and > tests ok (but it has little use while these ports remain out-of-tree). Not that I can approve this anyway, but: what are the properties of MODE_POINTER vs. MODE_PARTIAL_INT? It seems odd on the face of it for POINTER_MODE_P (Pmode) to be false on the majority of targets. But that's probably just a naming thing. Richard