* [RFC] Automatically generated DFA descriptions
@ 2004-07-10 12:40 Paolo Bonzini
2004-07-10 12:57 ` Richard Sandiford
0 siblings, 1 reply; 6+ messages in thread
From: Paolo Bonzini @ 2004-07-10 12:40 UTC (permalink / raw)
To: gcc-patches
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This patch updates the define_function_unit ports (MIPS and SH) to use
DFA-based descriptions. It is not complete as it only touches the MD
files (not the target hook); the interesting part is that after doing
the SHmedia I figured out how to automatically generate the MIPS
descriptions, and did so with a script that is included at the bottom
of the patch.
What it does is transforming an input, whose lines are CPU names or
all-on-one-line define_function_unit declarations, to a set of .md
files, each describing a different automaton based on the "cpu"
attribute.
Each function_unit is translated to many cpu_units, one for each
CPU that actually uses it. Issue delay are transformed into a regex,
while ready delays are transformed into latencies. A generic
reservation is emitted for uncovered instructions (based on the
"type" attribute) that reserves all the CPU units for a single
cycle and has a latency of 1.
The question is: how much sane does this look?
An auxiliary questions is: could we then remove define_function_unit
altogether instead of deprecating it?
Paolo
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2004-07-10 Paolo Bonzini <bonzini@gnu.org>
* config/mips/3000.md, config/mips/3900.md,
config/mips/4000.md, config/mips/4100.md,
config/mips/4120.md, config/mips/4300.md,
config/mips/4600.md, config/mips/4650.md,
config/mips/5000.md: New files.
* config/mips/mips.md: Include them, remove define_function_units.
* config/sh/shmedia.md: New file.
* config/sh/sh.md: Include it, remove define_function_units.
diff -rNu gcc-backup/gcc/config/mips/3000.md gcc-pass/gcc/config/mips/3000.md
--- gcc-backup/gcc/config/mips/3000.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/3000.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,71 @@
+;; DFA scheduling description for the MIPS R3000
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r3000")
+(define_cpu_unit "r3000_memory,r3000_imuldiv,r3000_adder,r3000_mult,r3000_divide" "r3000")
+
+(define_insn_reservation "r3000_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r3000"))
+ "r3000_memory*1")
+(define_insn_reservation "r3000_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r3000"))
+ "r3000_memory*1")
+(define_insn_reservation "r3000_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r3000"))
+ "r3000_memory*1")
+(define_insn_reservation "r3000_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r3000"))
+ "r3000_imuldiv*3")
+(define_insn_reservation "r3000_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r3000"))
+ "r3000_imuldiv*5")
+(define_insn_reservation "r3000_imuldiv" 12
+ (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3000"))
+ "r3000_imuldiv*12")
+(define_insn_reservation "r3000_imuldiv" 35
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000"))
+ "r3000_imuldiv*35")
+(define_insn_reservation "r3000_adder" 2
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000"))
+ "r3000_adder*1")
+(define_insn_reservation "r3000_adder" 2
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000"))
+ "r3000_adder*1")
+(define_insn_reservation "r3000_adder" 1
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3000"))
+ "r3000_adder*1")
+(define_insn_reservation "r3000_mult" 4
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
+ "r3000_mult*1")
+(define_insn_reservation "r3000_mult" 5
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
+ "r3000_mult*1")
+(define_insn_reservation "r3000_divide" 12
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
+ "r3000_divide*1")
+(define_insn_reservation "r3000_divide" 19
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
+ "r3000_divide*1")
+
+(define_insn_reservation "r3000_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv,fcmp,fadd,fabs,fneg,fmove,fmul,fdiv") (eq_attr "cpu" "r3000"))
+ "r3000_memory+r3000_imuldiv,r3000_adder,r3000_mult,r3000_divide")
diff -rNu gcc-backup/gcc/config/mips/3900.md gcc-pass/gcc/config/mips/3900.md
--- gcc-backup/gcc/config/mips/3900.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/3900.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,92 @@
+;; DFA scheduling description for the MIPS R3900
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r3900")
+(define_cpu_unit "r3900_memory,r3900_imuldiv,r3900_adder,r3900_mult,r3900_divide" "r3900")
+
+(define_insn_reservation "r3900_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r3900"))
+ "r3900_memory*1")
+(define_insn_reservation "r3900_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r3900"))
+ "r3900_memory*1")
+(define_insn_reservation "r3900_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r3900"))
+ "r3900_memory*1")
+(define_insn_reservation "r3900_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r3900"))
+ "r3900_imuldiv*3")
+(define_insn_reservation "r3900_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r3900"))
+ "r3900_imuldiv*5")
+(define_insn_reservation "r3900_imuldiv" 12
+ (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3900"))
+ "r3900_imuldiv*12")
+(define_insn_reservation "r3900_imuldiv" 35
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3900"))
+ "r3900_imuldiv*35")
+(define_insn_reservation "r3900_adder" 3
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900"))
+ "r3900_adder*1")
+(define_insn_reservation "r3900_adder" 2
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900"))
+ "r3900_adder*1")
+(define_insn_reservation "r3900_adder" 4
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900"))
+ "r3900_adder*1")
+(define_insn_reservation "r3900_adder" 2
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900"))
+ "r3900_adder*1")
+(define_insn_reservation "r3900_adder" 2
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3900"))
+ "r3900_adder*1")
+(define_insn_reservation "r3900_adder" 1
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3900"))
+ "r3900_adder*1")
+(define_insn_reservation "r3900_mult" 7
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900")))
+ "r3900_mult*1")
+(define_insn_reservation "r3900_mult" 4
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900")))
+ "r3900_mult*1")
+(define_insn_reservation "r3900_mult" 8
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900")))
+ "r3900_mult*1")
+(define_insn_reservation "r3900_mult" 5
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900")))
+ "r3900_mult*1")
+(define_insn_reservation "r3900_divide" 23
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900")))
+ "r3900_divide*1")
+(define_insn_reservation "r3900_divide" 12
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900")))
+ "r3900_divide*1")
+(define_insn_reservation "r3900_divide" 36
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900")))
+ "r3900_divide*1")
+(define_insn_reservation "r3900_divide" 19
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900")))
+ "r3900_divide*1")
+
+(define_insn_reservation "r3900_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv,fcmp,fadd,fabs,fneg,fmove,fmul,fdiv") (eq_attr "cpu" "r3900"))
+ "r3900_memory+r3900_imuldiv,r3900_adder,r3900_mult,r3900_divide")
diff -rNu gcc-backup/gcc/config/mips/4000.md gcc-pass/gcc/config/mips/4000.md
--- gcc-backup/gcc/config/mips/4000.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/4000.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,50 @@
+;; DFA scheduling description for the MIPS R4000
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r4000")
+(define_cpu_unit "r4000_memory,r4000_imuldiv" "r4000")
+
+(define_insn_reservation "r4000_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r4000"))
+ "r4000_memory*1")
+(define_insn_reservation "r4000_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r4000"))
+ "r4000_memory*1")
+(define_insn_reservation "r4000_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r4000"))
+ "r4000_memory*1")
+(define_insn_reservation "r4000_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r4000"))
+ "r4000_imuldiv*3")
+(define_insn_reservation "r4000_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r4000"))
+ "r4000_imuldiv*5")
+(define_insn_reservation "r4000_imuldiv" 10
+ (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4000"))
+ "r4000_imuldiv*10")
+(define_insn_reservation "r4000_imuldiv" 69
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
+ "r4000_imuldiv*69")
+
+(define_insn_reservation "r4000_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv") (eq_attr "cpu" "r4000"))
+ "r4000_memory+r4000_imuldiv")
diff -rNu gcc-backup/gcc/config/mips/4100.md gcc-pass/gcc/config/mips/4100.md
--- gcc-backup/gcc/config/mips/4100.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/4100.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,56 @@
+;; DFA scheduling description for the MIPS R4100
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r4100")
+(define_cpu_unit "r4100_memory,r4100_imuldiv" "r4100")
+
+(define_insn_reservation "r4100_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r4100"))
+ "r4100_memory*1")
+(define_insn_reservation "r4100_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r4100"))
+ "r4100_memory*1")
+(define_insn_reservation "r4100_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r4100"))
+ "r4100_memory*1")
+(define_insn_reservation "r4100_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r4100"))
+ "r4100_imuldiv*3")
+(define_insn_reservation "r4100_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r4100"))
+ "r4100_imuldiv*5")
+(define_insn_reservation "r4100_imuldiv" 1
+ (and (eq_attr "type" "imul,imadd") (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
+ "r4100_imuldiv*1")
+(define_insn_reservation "r4100_imuldiv" 4
+ (and (eq_attr "type" "imul,imadd") (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
+ "r4100_imuldiv*4")
+(define_insn_reservation "r4100_imuldiv" 35
+ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
+ "r4100_imuldiv*35")
+(define_insn_reservation "r4100_imuldiv" 67
+ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
+ "r4100_imuldiv*67")
+
+(define_insn_reservation "r4100_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv") (eq_attr "cpu" "r4100"))
+ "r4100_memory+r4100_imuldiv")
diff -rNu gcc-backup/gcc/config/mips/4120.md gcc-pass/gcc/config/mips/4120.md
--- gcc-backup/gcc/config/mips/4120.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/4120.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,56 @@
+;; DFA scheduling description for the MIPS R4120
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r4120")
+(define_cpu_unit "r4120_memory,r4120_imuldiv" "r4120")
+
+(define_insn_reservation "r4120_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r4120"))
+ "r4120_memory*1")
+(define_insn_reservation "r4120_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r4120"))
+ "r4120_memory*1")
+(define_insn_reservation "r4120_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r4120"))
+ "r4120_memory*1")
+(define_insn_reservation "r4120_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r4120"))
+ "r4120_imuldiv*3")
+(define_insn_reservation "r4120_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r4120"))
+ "r4120_imuldiv*5")
+(define_insn_reservation "r4120_imuldiv" 1
+ (and (eq_attr "type" "imul,imadd") (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4120")))
+ "r4120_imuldiv*1")
+(define_insn_reservation "r4120_imuldiv" 4
+ (and (eq_attr "type" "imul,imadd") (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4120")))
+ "r4120_imuldiv*4")
+(define_insn_reservation "r4120_imuldiv" 35
+ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4120")))
+ "r4120_imuldiv*35")
+(define_insn_reservation "r4120_imuldiv" 67
+ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4120")))
+ "r4120_imuldiv*67")
+
+(define_insn_reservation "r4120_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv") (eq_attr "cpu" "r4120"))
+ "r4120_memory+r4120_imuldiv")
diff -rNu gcc-backup/gcc/config/mips/4300.md gcc-pass/gcc/config/mips/4300.md
--- gcc-backup/gcc/config/mips/4300.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/4300.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,101 @@
+;; DFA scheduling description for the MIPS R4300
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r4300")
+(define_cpu_unit "r4300_memory,r4300_imuldiv,r4300_adder,r4300_mult,r4300_divide" "r4300")
+
+(define_insn_reservation "r4300_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r4300"))
+ "r4300_memory*1")
+(define_insn_reservation "r4300_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r4300"))
+ "r4300_memory*1")
+(define_insn_reservation "r4300_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r4300"))
+ "r4300_memory*1")
+(define_insn_reservation "r4300_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r4300"))
+ "r4300_imuldiv*3")
+(define_insn_reservation "r4300_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r4300"))
+ "r4300_imuldiv*5")
+(define_insn_reservation "r4300_imuldiv" 5
+ (and (eq_attr "type" "imul,imadd") (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
+ "r4300_imuldiv*5")
+(define_insn_reservation "r4300_imuldiv" 8
+ (and (eq_attr "type" "imul,imadd") (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
+ "r4300_imuldiv*8")
+(define_insn_reservation "r4300_imuldiv" 37
+ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
+ "r4300_imuldiv*37")
+(define_insn_reservation "r4300_imuldiv" 69
+ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
+ "r4300_imuldiv*69")
+(define_insn_reservation "r4300_adder" 3
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r4300"))
+ "r4300_adder*1")
+(define_insn_reservation "r4300_adder" 4
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
+ "r4300_adder*1")
+(define_insn_reservation "r4300_adder" 2
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r4300"))
+ "r4300_adder*1")
+(define_insn_reservation "r4300_mult" 7
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
+ "r4300_mult*1")
+(define_insn_reservation "r4300_mult" 8
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
+ "r4300_mult*1")
+(define_insn_reservation "r4300_divide" 23
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
+ "r4300_divide*1")
+(define_insn_reservation "r4300_divide" 36
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
+ "r4300_divide*1")
+(define_insn_reservation "r4300_divide" 54
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
+ "r4300_divide*1")
+(define_insn_reservation "r4300_divide" 112
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
+ "r4300_divide*1")
+(define_insn_reservation "r4300_imuldiv" 3
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
+ "r4300_imuldiv*3")
+(define_insn_reservation "r4300_imuldiv" 1
+ (and (eq_attr "type" "fcmp,fabs,fneg,fmove") (eq_attr "cpu" "r4300"))
+ "r4300_imuldiv*1")
+(define_insn_reservation "r4300_imuldiv" 5
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
+ "r4300_imuldiv*5")
+(define_insn_reservation "r4300_imuldiv" 8
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
+ "r4300_imuldiv*8")
+(define_insn_reservation "r4300_imuldiv" 29
+ (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt")) (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
+ "r4300_imuldiv*29")
+(define_insn_reservation "r4300_imuldiv" 58
+ (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt")) (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
+ "r4300_imuldiv*58")
+
+(define_insn_reservation "r4300_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv,fcmp,fadd,fabs,fneg,fmove,fmul,fdiv,fsqrt,frsqrt") (eq_attr "cpu" "r4300"))
+ "r4300_memory+r4300_imuldiv,r4300_adder,r4300_mult,r4300_divide")
diff -rNu gcc-backup/gcc/config/mips/4600.md gcc-pass/gcc/config/mips/4600.md
--- gcc-backup/gcc/config/mips/4600.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/4600.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,80 @@
+;; DFA scheduling description for the MIPS R4600
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r4600")
+(define_cpu_unit "r4600_memory,r4600_imuldiv,r4600_adder,r4600_mult,r4600_divide" "r4600")
+
+(define_insn_reservation "r4600_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r4600"))
+ "r4600_memory*1")
+(define_insn_reservation "r4600_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r4600"))
+ "r4600_memory*1")
+(define_insn_reservation "r4600_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r4600"))
+ "r4600_memory*1")
+(define_insn_reservation "r4600_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r4600"))
+ "r4600_imuldiv*3")
+(define_insn_reservation "r4600_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r4600"))
+ "r4600_imuldiv*5")
+(define_insn_reservation "r4600_imuldiv" 10
+ (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4600"))
+ "r4600_imuldiv*10")
+(define_insn_reservation "r4600_imuldiv" 42
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
+ "r4600_imuldiv*42")
+(define_insn_reservation "r4600_adder" 2
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r4600"))
+ "r4600_adder*1")
+(define_insn_reservation "r4600_adder" 1
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r4600"))
+ "r4600_adder*1")
+(define_insn_reservation "r4600_mult" 7
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
+ "r4600_mult*1")
+(define_insn_reservation "r4600_mult" 8
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
+ "r4600_mult*1")
+(define_insn_reservation "r4600_divide" 23
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
+ "r4600_divide*1")
+(define_insn_reservation "r4600_divide" 32
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
+ "r4600_divide*1")
+(define_insn_reservation "r4600_divide" 36
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600")))
+ "r4600_divide*1")
+(define_insn_reservation "r4600_divide" 61
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600")))
+ "r4600_divide*1")
+(define_insn_reservation "r4600_divide" 31
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
+ "r4600_divide*1")
+(define_insn_reservation "r4600_divide" 60
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600")))
+ "r4600_divide*1")
+
+(define_insn_reservation "r4600_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv,fabs,fneg,fmove,fmul,fdiv,fsqrt,frsqrt") (eq_attr "cpu" "r4600"))
+ "r4600_memory+r4600_imuldiv,r4600_adder,r4600_mult,r4600_divide")
diff -rNu gcc-backup/gcc/config/mips/4650.md gcc-pass/gcc/config/mips/4650.md
--- gcc-backup/gcc/config/mips/4650.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/4650.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,86 @@
+;; DFA scheduling description for the MIPS R4650
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r4650")
+(define_cpu_unit "r4650_memory,r4650_imuldiv,r4650_adder,r4650_mult,r4650_divide" "r4650")
+
+(define_insn_reservation "r4650_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r4650"))
+ "r4650_memory*1")
+(define_insn_reservation "r4650_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r4650"))
+ "r4650_memory*1")
+(define_insn_reservation "r4650_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r4650"))
+ "r4650_memory*1")
+(define_insn_reservation "r4650_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r4650"))
+ "r4650_imuldiv*3")
+(define_insn_reservation "r4650_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r4650"))
+ "r4650_imuldiv*5")
+(define_insn_reservation "r4650_imuldiv" 4
+ (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4650"))
+ "r4650_imuldiv*4")
+(define_insn_reservation "r4650_imuldiv" 36
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
+ "r4650_imuldiv*36")
+(define_insn_reservation "r4650_adder" 2
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r4650"))
+ "r4650_adder*1")
+(define_insn_reservation "r4650_adder" 1
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r4650"))
+ "r4650_adder*1")
+(define_insn_reservation "r4650_mult" 7
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4650")))
+ "r4650_mult*1")
+(define_insn_reservation "r4650_mult" 8
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4650")))
+ "r4650_mult*1")
+(define_insn_reservation "r4650_divide" 23
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4650")))
+ "r4650_divide*1")
+(define_insn_reservation "r4650_divide" 32
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4650")))
+ "r4650_divide*1")
+(define_insn_reservation "r4650_divide" 36
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4650")))
+ "r4650_divide*1")
+(define_insn_reservation "r4650_divide" 61
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4650")))
+ "r4650_divide*1")
+(define_insn_reservation "r4650_divide" 54
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4650")))
+ "r4650_divide*1")
+(define_insn_reservation "r4650_divide" 31
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4650")))
+ "r4650_divide*1")
+(define_insn_reservation "r4650_divide" 112
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4650")))
+ "r4650_divide*1")
+(define_insn_reservation "r4650_divide" 60
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4650")))
+ "r4650_divide*1")
+
+(define_insn_reservation "r4650_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv,fabs,fneg,fmove,fmul,fdiv,fsqrt,frsqrt") (eq_attr "cpu" "r4650"))
+ "r4650_memory+r4650_imuldiv,r4650_adder,r4650_mult,r4650_divide")
diff -rNu gcc-backup/gcc/config/mips/5000.md gcc-pass/gcc/config/mips/5000.md
--- gcc-backup/gcc/config/mips/5000.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/mips/5000.md 2004-07-10 00:33:31.000000000 +0200
@@ -0,0 +1,98 @@
+;; DFA scheduling description for the MIPS R5000
+;; Copyright (C) 2004 Free Software Foundation
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; This is just a translation of the old define_function_unit description
+
+(define_automaton "r5000")
+(define_cpu_unit "r5000_memory,r5000_imuldiv,r5000_adder,r5000_mult,r5000_divide" "r5000")
+
+(define_insn_reservation "r5000_memory" 2
+ (and (eq_attr "type" "load,fpload,fpidxload") (eq_attr "cpu" "r5000"))
+ "r5000_memory*1")
+(define_insn_reservation "r5000_memory" 1
+ (and (eq_attr "type" "store,fpstore,fpidxstore") (eq_attr "cpu" "r5000"))
+ "r5000_memory*1")
+(define_insn_reservation "r5000_memory" 2
+ (and (eq_attr "type" "xfer") (eq_attr "cpu" "r5000"))
+ "r5000_memory*1")
+(define_insn_reservation "r5000_imuldiv" 1
+ (and (eq_attr "type" "mthilo,mfhilo") (eq_attr "cpu" "r5000"))
+ "r5000_imuldiv*3")
+(define_insn_reservation "r5000_imuldiv" 1
+ (and (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (eq_attr "cpu" "r5000"))
+ "r5000_imuldiv*5")
+(define_insn_reservation "r5000_imuldiv" 5
+ (and (eq_attr "type" "imul,imadd") (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
+ "r5000_imuldiv*5")
+(define_insn_reservation "r5000_imuldiv" 9
+ (and (eq_attr "type" "imul,imadd") (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
+ "r5000_imuldiv*9")
+(define_insn_reservation "r5000_imuldiv" 36
+ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
+ "r5000_imuldiv*36")
+(define_insn_reservation "r5000_imuldiv" 68
+ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
+ "r5000_imuldiv*68")
+(define_insn_reservation "r5000_adder" 3
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
+ "r5000_adder*1")
+(define_insn_reservation "r5000_adder" 1
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
+ "r5000_adder*1")
+(define_insn_reservation "r5000_adder" 2
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r5000"))
+ "r5000_adder*1")
+(define_insn_reservation "r5000_adder" 1
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r5000"))
+ "r5000_adder*1")
+(define_insn_reservation "r5000_mult" 7
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
+ "r5000_mult*1")
+(define_insn_reservation "r5000_mult" 4
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
+ "r5000_mult*1")
+(define_insn_reservation "r5000_mult" 8
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
+ "r5000_mult*1")
+(define_insn_reservation "r5000_mult" 5
+ (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
+ "r5000_mult*1")
+(define_insn_reservation "r5000_divide" 23
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
+ "r5000_divide*1")
+(define_insn_reservation "r5000_divide" 21
+ (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
+ "r5000_divide*1")
+(define_insn_reservation "r5000_divide" 54
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
+ "r5000_divide*1")
+(define_insn_reservation "r5000_divide" 21
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
+ "r5000_divide*1")
+(define_insn_reservation "r5000_divide" 112
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
+ "r5000_divide*1")
+(define_insn_reservation "r5000_divide" 36
+ (and (eq_attr "type" "fsqrt,frsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
+ "r5000_divide*1")
+
+(define_insn_reservation "r5000_all" 1
+ (and (eq_attr "type" "!load,fpload,fpidxload,store,fpstore,fpidxstore,xfer,mthilo,mfhilo,imul,imadd,idiv,fcmp,fabs,fneg,fmove,fmul,fdiv,fsqrt,frsqrt") (eq_attr "cpu" "r5000"))
+ "r5000_memory+r5000_imuldiv,r5000_adder,r5000_mult,r5000_divide")
diff -rNu gcc-backup/gcc/config/mips/mips.md gcc-pass/gcc/config/mips/mips.md
--- gcc-backup/gcc/config/mips/mips.md 2004-06-16 19:19:40.000000000 +0200
+++ gcc-pass/gcc/config/mips/mips.md 2004-07-10 00:41:55.000000000 +0200
@@ -313,325 +313,18 @@
(nil)
(nil)])
\f
-;; .........................
-;;
-;; Functional units
-;;
-;; .........................
-
-; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
-; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-
-;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
-
-(define_function_unit "memory" 1 0
- (and (eq_attr "type" "load,fpload,fpidxload")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
- 3 0)
-
-(define_function_unit "memory" 1 0
- (and (eq_attr "type" "load,fpload,fpidxload")
- (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
- 2 0)
-
-(define_function_unit "memory" 1 0
- (eq_attr "type" "store,fpstore,fpidxstore")
- 1 0)
-
-(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
-
-(define_function_unit "imuldiv" 1 0
- (eq_attr "type" "mthilo,mfhilo")
- 1 3)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
- 17 17)
-
-;; On them mips16, we want to stronly discourage a mult from appearing
-;; after an mflo, since that requires explicit nop instructions. We
-;; do this by pretending that mflo ties up the function unit for long
-;; enough that the scheduler will ignore load stalls and the like when
-;; selecting instructions to between the two instructions.
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
- 1 5)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3000,r3900"))
- 12 12)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4000,r4600"))
- 10 10)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4650"))
- 4 4)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
- 1 1)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
- 4 4)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
- 5 5)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
- 8 8)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
- 9 9)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
- 38 38)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
- 35 35)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
- 42 42)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
- 36 36)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
- 69 69)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
- 35 35)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
- 67 67)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
- 37 37)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
- 69 69)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
- 36 36)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
- 68 68)
-
-;; The R4300 does *NOT* have a separate Floating Point Unit, instead
-;; the FP hardware is part of the normal ALU circuitry. This means FP
-;; instructions affect the pipe-line, and no functional unit
-;; parallelism can occur on R4300 processors. To force GCC into coding
-;; for only a single functional unit, we force the R4300 FP
-;; instructions to be processed in the "imuldiv" unit.
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
- 3 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
- 2 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
- 1 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
- 4 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
- 2 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
- 3 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg,fmove")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
- 2 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
- 1 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
- 7 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
- 4 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
- 5 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 8 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
- 8 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
- 5 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
- 6 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
- 23 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
- 12 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
- 15 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 32 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
- 21 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
- 36 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
- 19 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
- 16 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
- 61 0)
-
-;;; ??? Is this number right?
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
- 54 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 31 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
- 21 0)
-
-;;; ??? Is this number right?
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
- 112 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
- 60 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
- 36 0)
-
-;; R4300 FP instruction classes treated as part of the "imuldiv"
-;; functional unit:
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
- 3 3)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fcmp,fabs,fneg,fmove") (eq_attr "cpu" "r4300"))
- 1 1)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
- 5 5)
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
- 8 8)
-
-(define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
- 29 29)
-(define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
- 58 58)
-\f
;; Include scheduling descriptions.
+(include "3000.md")
+(include "3900.md")
+(include "4000.md")
+(include "4100.md")
+(include "4120.md")
(include "4130.md")
+(include "4300.md")
+(include "4600.md")
+(include "4650.md")
+(include "5000.md")
(include "5400.md")
(include "5500.md")
(include "7000.md")
diff -rNu gcc-backup/gcc/config/sh/sh.md gcc-pass/gcc/config/sh/sh.md
--- gcc-backup/gcc/config/sh/sh.md 2004-06-16 19:19:52.000000000 +0200
+++ gcc-pass/gcc/config/sh/sh.md 2004-07-09 23:40:27.000000000 +0200
@@ -470,64 +470,7 @@
(define_function_unit "fp" 1 0
(and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fdiv")) 13 12)
-
-;; SH-5 SHmedia scheduling
-;; When executing SHmedia code, the SH-5 is a fairly straightforward
-;; single-issue machine. It has four pipelines, the branch unit (br),
-;; the integer and multimedia unit (imu), the load/store unit (lsu), and
-;; the floating point unit (fpu).
-;; Here model the instructions with a latency greater than one cycle.
-
-;; Every instruction on SH-5 occupies the issue resource for at least one
-;; cycle.
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "!pt_media,ptabs_media,invalidate_line_media,dmpy_media,load_media,fload_media,fcmp_media,fmove_media,fparith_media,dfparith_media,fpconv_media,dfpconv_media,dfmul_media,store_media,fstore_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media")) 1 1)
-
-;; Specify the various types of instruction which have latency > 1
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "mcmp_media")) 2 1)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "dmpy_media,load_media,fcmp_media,mac_media")) 3 1)
-;; but see sh_adjust_cost for mac_media exception.
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "fload_media,fmove_media")) 4 1)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "d2mpy_media")) 4 2)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "pt_media,ptabs_media")) 5 1)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "fparith_media,dfparith_media,fpconv_media,dfpconv_media")) 6 1)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "invalidate_line_media")) 7 7)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfmul_media")) 9 4)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "atrans_media")) 10 5)
-
-;; Floating-point divide and square-root occupy an additional resource,
-;; which is not internally pipelined. However, other instructions
-;; can continue to issue.
-(define_function_unit "sh5fds" 1 0
- (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media")) 19 19)
-
-(define_function_unit "sh5fds" 1 0
- (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media")) 35 35)
+(include "shmedia.md")
; Definitions for filling branch delay slots.
diff -rNu gcc-backup/gcc/config/sh/shmedia.md gcc-pass/gcc/config/sh/shmedia.md
--- gcc-backup/gcc/config/sh/shmedia.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-pass/gcc/config/sh/shmedia.md 2004-07-09 23:39:49.000000000 +0200
@@ -0,0 +1,92 @@
+;;- DFA scheduling description for SH-5 SHmedia instructions.
+;; Copyright (C) 2004 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; When executing SHmedia code, the SH-5 is a fairly straightforward
+;; single-issue machine. It has four pipelines, the branch unit (br),
+;; the integer and multimedia unit (imu), the load/store unit (lsu), and
+;; the floating point unit (fpu).
+;; Here model the instructions with a latency greater than one cycle.
+
+;; Every instruction on SH-5 occupies the issue resource for at least one
+;; cycle.
+(define_automaton "shmedia")
+
+(define_cpu_unit "sh5issue,sh5fds" "shmedia")
+
+(define_insn_reservation "shmedia1" 1
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "!pt_media,ptabs_media,invalidate_line_media,dmpy_media,load_media,fload_media,fcmp_media,fmove_media,fparith_media,dfparith_media,fpconv_media,dfpconv_media,dfmul_media,store_media,fstore_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media"))
+ "sh5issue")
+
+;; Specify the various types of instruction which have latency > 1
+(define_insn_reservation "shmedia2" 2
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "mcmp_media"))
+ "sh5issue")
+
+(define_insn_reservation "shmedia3" 3
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "dmpy_media,load_media,fcmp_media,mac_media"))
+ "sh5issue")
+;; but see sh_adjust_cost for mac_media exception.
+
+(define_insn_reservation "shmedia4" 4
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "fload_media,fmove_media"))
+ "sh5issue")
+
+(define_insn_reservation "shmedia_d2mpy" 4
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "d2mpy_media"))
+ "sh5issue*2")
+
+(define_insn_reservation "shmedia5" 5
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "pt_media,ptabs_media"))
+ "sh5issue")
+
+(define_insn_reservation "shmedia6" 6
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "fparith_media,dfparith_media,fpconv_media,dfpconv_media"))
+ "sh5issue")
+
+(define_insn_reservation "shmedia_invalidate" 7
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "invalidate_line_media"))
+ "sh5issue*7")
+
+(define_insn_reservation "shmedia_dfmul" 9
+ (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfmul_media"))
+ "sh5issue*4")
+
+(define_insn_reservation "shmedia_atrans" 10
+ (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "atrans_media"))
+ "sh5issue*5")
+
+;; Floating-point divide and square-root occupy an additional resource,
+;; which is not internally pipelined. However, other instructions
+;; can continue to issue.
+(define_insn_reservation "shmedia_fdiv" 19
+ (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media"))
+ "sh5fds*19")
+
+(define_insn_reservation "shmedia_dfdiv" 35
+ (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media"))
+ "sh5fds*35")
# Record the name of a CPU
!/^\(/ {
cpu_list[$1] = ""
}
# Record a define_function_unit
/^\(/ {
# Convert the issue delay to a number, and unquote the unit name
gsub (/\)$/, "", $NF)
gsub (/"/, "", $2)
# Look for the "cpu" and "type" attributes. "cpu" can be negated,
# while "type" cannot
field_cpu = -1
for (i = 5; i < NF; i++)
if ($i == "\"cpu\"")
{
if ($(i+1) ~ /^!/)
$(i+1) = q(neg_array(substr ($(i+1), 2), cpu_list))
cpus = $(i+1)
field_cpu = i+1
break
}
else if ($i == "\"type\"")
types = $(i+1)
# Extract more stuff from define_function_unit
unit = $2
latency = $(NF-1)
issue_delay = $NF == 0 ? 1 : $NF
# Clean up the info
gsub (/"/, ",", cpus)
gsub (/[")]/, "", types)
# Extract the attributes test
$1 = ""
$2 = ""
$3 = ""
$4 = ""
$(NF-1) = ""
$(NF) = ""
attrs = squeeze($0)
# For all the CPUs, add a define_insn_reservation if needed
for (i in cpu_list)
{
if (field_cpu == -1)
{
# No cpu attribute? Add it
$0 = "(and " attrs " (eq_attr \"cpu\" " q(i) "))"
}
else if (cpus ~ ("," i ","))
{
# If there was a cpu attribute, replace it
$0 = attrs
sub (/"cpu" "[^"]*"/, "\"cpu\" " q(i))
}
else
continue
# Build parts of the define_insn_reservations
cpu_unit = i "_" unit
regex = q(cpu_unit "*" issue_delay)
# Save what will go in define_cpu_unit
if (!(cpu_unit in cpu_units))
{
cpu_units[cpu_unit] = ""
define_cpu_units[i] = define_cpu_units[i] "," cpu_unit
}
# Add to the specialized insn types, so that we'll specify a latency of 1
cpu_types[i] = cpu_types[i] "," types
define_insn_reservations[i] = define_insn_reservations[i] "\n\
(define_insn_reservation " q(cpu_unit) " " latency "\n\
" $0 "\n\
" regex ")"
}
}
END {
for (i in cpu_list)
{
define_cpu_units[i] = substr (define_cpu_units[i], 2)
# Build parts of the generic define_insn_reservation
all_cpu_units = define_cpu_units[i]
gsub (/,/, "+", all_cpu_units)
types = remove_dups(substr (cpu_types[i], 2))
print ";; DFA scheduling description for the MIPS R" substr (i, 2) "\n\
;; Copyright (C) 2004 Free Software Foundation\n\
\n\
;; This file is part of GCC.\n\
\n\
;; GCC is free software; you can redistribute it and/or modify\n\
;; it under the terms of the GNU General Public License as published by\n\
;; the Free Software Foundation; either version 2, or (at your option)\n\
;; any later version.\n\
\n\
;; GCC is distributed in the hope that it will be useful,\n\
;; but WITHOUT ANY WARRANTY; without even the implied warranty of\n\
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n\
;; GNU General Public License for more details.\n\
\n\
;; You should have received a copy of the GNU General Public License\n\
;; along with GCC; see the file COPYING. If not, write to\n\
;; the Free Software Foundation, 59 Temple Place - Suite 330,\n\
;; Boston, MA 02111-1307, USA.\n\
\n\
;; This is just a translation of the old define_function_unit description\n\n\
(define_automaton " q(i) ")\n\
(define_cpu_unit " q(define_cpu_units[i]) " " q(i) ")\n\
" define_insn_reservations[i] "\n\
\n\
(define_insn_reservation " q(i "_all") " 1\n\
(and (eq_attr \"type\" " q("!" types) ") (eq_attr \"cpu\" " q(i) "))\n\
" q(all_cpu_units) ")" > i ".md"
}
}
function q(s)
{
return "\"" s "\""
}
# Compute the complement of the comma-separated list N, with respect to LIST
function neg_array(n, list, save, j, neg_list)
{
save = $0
$0 = n
sub (/,/, " ", $0)
neg_list = list
for (j = 1; j < NF; j++)
delete neg_list[$j]
result = ""
for (j in neg_list)
result = result "," j
$0 = save
return substr (result, 2)
}
# Squeeze multiple spaces in N, and remove leading/trailing ones, returning
# the result
function squeeze(n)
{
gsub (/[ \t]+/, " ", n)
gsub (/^ /, "", n)
gsub (/ $/, "", n)
return n
}
# Remove duplicates from the comma-separated list N
function remove_dups(n, save, j, the_list)
{
save = $0
$0 = n
gsub (/,/, " ", $0)
result = ""
for (j = 1; j <= NF; j++) {
if (!($j in the_list))
result = result "," $j
the_list[$j] = ""
}
$0 = save
return substr (result, 2)
}
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC] Automatically generated DFA descriptions
2004-07-10 12:40 [RFC] Automatically generated DFA descriptions Paolo Bonzini
@ 2004-07-10 12:57 ` Richard Sandiford
2004-07-10 16:09 ` Remove MIPS define_function_units Richard Sandiford
0 siblings, 1 reply; 6+ messages in thread
From: Richard Sandiford @ 2004-07-10 12:57 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: gcc-patches
Paolo Bonzini <bonzini@gnu.org> writes:
> 2004-07-10 Paolo Bonzini <bonzini@gnu.org>
>
> * config/mips/3000.md, config/mips/3900.md,
> config/mips/4000.md, config/mips/4100.md,
> config/mips/4120.md, config/mips/4300.md,
> config/mips/4600.md, config/mips/4650.md,
> config/mips/5000.md: New files.
> * config/mips/mips.md: Include them, remove define_function_units.
FWIW, the r3000 conversion is already done:
2004-06-23 Eric Christopher <echristo@redhat.com>
* config/mips/mips.c (mips_use_dfa_pipeline_interface): Add R3000.
* config/mips/mips.md: Remove R3000 scheduling description.
* config/mips/3000.md: New file.
But your automatically-generated files look like a very good
starting point for the rest. Thanks a lot for doing this!
If you don't mind, I'd still prefer to clean up and double-check the
new files by hand before applying them. I'll try to do it this weekend.
For example, with the r3000, we eventually got to a situation where the
DFA description produced no change in output over the define_function_unit
one. I'd like to verify that the same is true for the others as well.
There's also a few formatting glitches and redundant checks for mips16
(on processors that don't support it). We'll probably want to use
separate automata for imuldiv units, etc.
BTW, as a general comment: I'm a bit worried that after a full transition
to DFA, we're going to have lots of automata in the MIPS port. More than
30, at a guess. Each call to state_transition() will have to step every
automata, even though only a handful of states are actually of any use.
I was thinking we should have some way of identifying attributes like
"cpu" as run-time constants, and that we could have separate state_reset()/
state_transition() functions for each cpu. Anyone looking at this?
Richard
^ permalink raw reply [flat|nested] 6+ messages in thread
* Remove MIPS define_function_units
2004-07-10 12:57 ` Richard Sandiford
@ 2004-07-10 16:09 ` Richard Sandiford
2004-07-10 18:29 ` Eric Christopher
2004-07-10 18:31 ` Eric Christopher
0 siblings, 2 replies; 6+ messages in thread
From: Richard Sandiford @ 2004-07-10 16:09 UTC (permalink / raw)
To: Paolo Bonzini, echristo; +Cc: gcc-patches
Richard Sandiford <rsandifo@redhat.com> writes:
> BTW, as a general comment: I'm a bit worried that after a full transition
> to DFA, we're going to have lots of automata in the MIPS port. More than
> 30, at a guess. Each call to state_transition() will have to step every
> automata, even though only a handful of states are actually of any use.
...and I'd therefore like to take a different approach.
The old scheduler had just one set of units (alu, memory, adder, etc.)
and these units were used for all processors. For the reasons given
above, I don't think it's worth going away from that and creating
different cpu units and automata for each processor.
Also, there was a great deal of commonality between the schedulers.
I therefore don't think it's worth making every processor's .md file
specify something for every insn type. Instead, I'd like to use a
"generic" scheduler, placed at the end of the include list, and override
bits of it on a target-by-target basis.
So... the patch below extracts the old "default" scheduler: i.e. the
bits that were selected with (eq_attr "cpu" "!...."), or that had no
(eq_attr "cpu" ...) clause at all. This is the scheduler was used for
untuned processors like the 4kc, 5kc, etc. It goes in generic.md and
is included after all the other schedulers.
The patch then adds a new file for each processor that had been tuned.
These files override the parts of generic.md that don't apply.
This approach does mean that you have to look in two places if you want
to know how a particular processor is scheduled. I don't see that as
any great hardship, though, since its obvious at a glance which bits
have been overridden and which haven't.
IMO, the downside of having to look in two places is far outweighed by
the reduction in code duplication. Anyone who's actually interested in
the performance of these processors would probably be better off
starting from scratch anyway...
There were (at least) two major problems with the old description:
- fmadd instructions weren't handled, and were therefore treated like
single-cycle ALU operations. The patch treats them like fmul insns
instead.
I can't guarantee that the new behaviour is accurate for all processors,
but it's surely going to be an improvement over the single-cycle
assumption.
- The 4300.md description had:
(define_function_unit "imuldiv" 1 0
(and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
^^^^
(and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
29 29)
(define_function_unit "imuldiv" 1 0
(and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
^^^^
(and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
58 58)
which would clearly never be used. fdiv, fsqrt and frsqrt were therefore
treated as single-cycle ALU operations, just like fmadd. I'm assuming
the "and" should have been an "ior".
Tested by compiling C-torture at -O2 for each of the following processors:
4kc r3000 r3900 r4000 r4100 r4111 r4120 r4300 r4600
r4650 r5000 r6000 r8000
and comparing the assembly output before and after the patch. Because of
the problems mentioned above, there were differences in the output for
r4300, r5000 and r8000, the last two of which allow fmadd-type insns.
The output for the other processors didn't change.
As a sanity check, I tried treating fmadd and r4300 fdiv, fsqrt and
frsqrt insns as single-cycle ALU operations. There were then no changes
at all with the new description.
I'll run this through the usual bootstrap tests once the varargs stuff
has finished. Eric, is the patch OK with you?
Richard
* config/mips/mips.c (mips_use_dfa_pipeline_interface): Delete.
(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define to hook_int_void_1.
* config/mips/3000.md: Add copyright notice. Remove automota and
function units; use generic ones instead. Only define reservations
for things that are different from generic.md. Extend each clause
to include r3900.
* config/mips/{4000,4100,4300,4600,5000,6000,generic}.md: New files.
* config/mips/mips.md: Include them. Remove define_function_units.
(alu, imuldiv): New automata and units.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.426
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.426 mips.c
*** config/mips/mips.c 7 Jul 2004 19:24:28 -0000 1.426
--- config/mips/mips.c 10 Jul 2004 12:47:34 -0000
*************** static int mips_sched_reorder (FILE *, i
*** 283,289 ****
static int mips_variable_issue (FILE *, int, rtx, int);
static int mips_adjust_cost (rtx, rtx, rtx, int);
static int mips_issue_rate (void);
- static int mips_use_dfa_pipeline_interface (void);
static int mips_multipass_dfa_lookahead (void);
static void mips_init_libfuncs (void);
static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
--- 283,288 ----
*************** #define TARGET_SCHED_ADJUST_COST mips_ad
*** 732,738 ****
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
! #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
mips_multipass_dfa_lookahead
--- 731,737 ----
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
! #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
mips_multipass_dfa_lookahead
*************** mips_issue_rate (void)
*** 9924,9952 ****
}
- /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
- processors that have a DFA pipeline description. */
-
- static int
- mips_use_dfa_pipeline_interface (void)
- {
- switch (mips_tune)
- {
- case PROCESSOR_R3000:
- case PROCESSOR_R4130:
- case PROCESSOR_R5400:
- case PROCESSOR_R5500:
- case PROCESSOR_R7000:
- case PROCESSOR_R9000:
- case PROCESSOR_SB1:
- case PROCESSOR_SR71000:
- return true;
-
- default:
- return false;
- }
- }
-
/* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
be as wide as the scheduling freedom in the DFA. */
--- 9923,9928 ----
Index: config/mips/3000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/3000.md,v
retrieving revision 1.2
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.2 3000.md
*** config/mips/3000.md 30 Jun 2004 17:27:54 -0000 1.2
--- config/mips/3000.md 10 Jul 2004 12:47:34 -0000
***************
*** 1,78 ****
! ;; DFA based pipeline description for the r3000
! ;; This is a special pipeline - this is also the default schedule and
! ;; so we need to schedule instructions that may not exist on the r2k/r3k.
!
! (define_automaton "r3k_alu,r3k_imuldiv")
!
! (define_cpu_unit "r3k_alu" "r3k_alu")
! (define_cpu_unit "r3k_imuldiv" "r3k_imuldiv")
!
! (define_insn_reservation "r3k_generic" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith,
! shift,slt,clz,trap,multi,nop"))
! "r3k_alu")
(define_insn_reservation "r3k_load" 2
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "load,fpload,fpidxload,xfer"))
! "r3k_alu")
!
! (define_insn_reservation "r3k_store" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "store,fpstore,fpidxstore"))
! "r3k_alu")
!
! (define_insn_reservation "r3k_branch" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "branch,jump,call"))
! "r3k_alu")
!
! (define_insn_reservation "r3k_hilo" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "mfhilo,mthilo"))
! "r3k_imuldiv*3")
(define_insn_reservation "r3k_imul" 12
! (and (eq_attr "cpu" "r3000")
(eq_attr "type" "imul,imadd"))
! "r3k_imuldiv*12")
(define_insn_reservation "r3k_idiv" 35
! (and (eq_attr "cpu" "r3000")
(eq_attr "type" "idiv"))
! "r3k_imuldiv*35")
(define_insn_reservation "r3k_fmove" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "fabs,fneg,fmove,fcvt"))
! "r3k_alu")
(define_insn_reservation "r3k_fadd" 2
! (and (eq_attr "cpu" "r3000")
(eq_attr "type" "fcmp,fadd"))
! "r3k_alu")
(define_insn_reservation "r3k_fmul_single" 4
! (and (eq_attr "cpu" "r3000")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
! "r3k_alu")
(define_insn_reservation "r3k_fmul_double" 5
! (and (eq_attr "cpu" "r3000")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
! "r3k_alu")
(define_insn_reservation "r3k_fdiv_single" 12
! (and (eq_attr "cpu" "r3000")
! (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
(eq_attr "mode" "SF")))
! "r3k_alu")
(define_insn_reservation "r3k_fdiv_double" 19
! (and (eq_attr "cpu" "r3000")
! (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
(eq_attr "mode" "DF")))
! "r3k_alu")
--- 1,72 ----
! ;; R3000 and TX39 pipeline description.
! ;; Copyright (C) 2004 Free Software Foundation, Inc.
! ;;
! ;; This file is part of GCC.
!
! ;; GCC is free software; you can redistribute it and/or modify it
! ;; under the terms of the GNU General Public License as published
! ;; by the Free Software Foundation; either version 2, or (at your
! ;; option) any later version.
!
! ;; GCC is distributed in the hope that it will be useful, but WITHOUT
! ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
! ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
! ;; License for more details.
!
! ;; You should have received a copy of the GNU General Public License
! ;; along with GCC; see the file COPYING. If not, write to the
! ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
! ;; MA 02111-1307, USA.
!
!
! ;; This file overrides parts of generic.md. It is derived from the
! ;; old define_function_unit description.
(define_insn_reservation "r3k_load" 2
! (and (eq_attr "cpu" "r3000,r3900")
! (eq_attr "type" "load,fpload,fpidxload"))
! "alu")
(define_insn_reservation "r3k_imul" 12
! (and (eq_attr "cpu" "r3000,r3900")
(eq_attr "type" "imul,imadd"))
! "imuldiv*12")
(define_insn_reservation "r3k_idiv" 35
! (and (eq_attr "cpu" "r3000,r3900")
(eq_attr "type" "idiv"))
! "imuldiv*35")
(define_insn_reservation "r3k_fmove" 1
! (and (eq_attr "cpu" "r3000,r3900")
! (eq_attr "type" "fabs,fneg,fmove"))
! "alu")
(define_insn_reservation "r3k_fadd" 2
! (and (eq_attr "cpu" "r3000,r3900")
(eq_attr "type" "fcmp,fadd"))
! "alu")
(define_insn_reservation "r3k_fmul_single" 4
! (and (eq_attr "cpu" "r3000,r3900")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
! "alu")
(define_insn_reservation "r3k_fmul_double" 5
! (and (eq_attr "cpu" "r3000,r3900")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
! "alu")
(define_insn_reservation "r3k_fdiv_single" 12
! (and (eq_attr "cpu" "r3000,r3900")
! (and (eq_attr "type" "fdiv")
(eq_attr "mode" "SF")))
! "alu")
(define_insn_reservation "r3k_fdiv_double" 19
! (and (eq_attr "cpu" "r3000,r3900")
! (and (eq_attr "type" "fdiv")
(eq_attr "mode" "DF")))
! "alu")
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.250
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.250 mips.md
*** config/mips/mips.md 7 Jul 2004 19:24:31 -0000 1.250
--- config/mips/mips.md 10 Jul 2004 12:47:35 -0000
*************** (define_delay (and (eq_attr "type" "call
*** 313,644 ****
(nil)
(nil)])
\f
! ;; .........................
! ;;
! ;; Functional units
! ;;
! ;; .........................
! ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
! ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
- ;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
-
- (define_function_unit "memory" 1 0
- (and (eq_attr "type" "load,fpload,fpidxload")
- (eq_attr "cpu" "!r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
- 3 0)
-
- (define_function_unit "memory" 1 0
- (and (eq_attr "type" "load,fpload,fpidxload")
- (eq_attr "cpu" "r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
- 2 0)
-
- (define_function_unit "memory" 1 0
- (eq_attr "type" "store,fpstore,fpidxstore")
- 1 0)
-
- (define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
-
- (define_function_unit "imuldiv" 1 0
- (eq_attr "type" "mthilo,mfhilo")
- 1 3)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (eq_attr "cpu" "!r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
- 17 17)
-
- ;; On them mips16, we want to stronly discourage a mult from appearing
- ;; after an mflo, since that requires explicit nop instructions. We
- ;; do this by pretending that mflo ties up the function unit for long
- ;; enough that the scheduler will ignore load stalls and the like when
- ;; selecting instructions to between the two instructions.
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
- 1 5)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3900"))
- 12 12)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4000,r4600"))
- 10 10)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4650"))
- 4 4)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
- 1 1)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
- 4 4)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
- 5 5)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
- 8 8)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
- 9 9)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (eq_attr "cpu" "!r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
- 38 38)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3900"))
- 35 35)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
- 42 42)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
- 36 36)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
- 69 69)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
- 35 35)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
- 67 67)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
- 37 37)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
- 69 69)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
- 36 36)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
- 68 68)
-
- ;; The R4300 does *NOT* have a separate Floating Point Unit, instead
- ;; the FP hardware is part of the normal ALU circuitry. This means FP
- ;; instructions affect the pipe-line, and no functional unit
- ;; parallelism can occur on R4300 processors. To force GCC into coding
- ;; for only a single functional unit, we force the R4300 FP
- ;; instructions to be processed in the "imuldiv" unit.
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3900,r6000,r4300,r5000"))
- 3 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900,r6000"))
- 2 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
- 1 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3900,r6000,r4300"))
- 4 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900"))
- 2 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
- 3 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg,fmove")
- (eq_attr "cpu" "!r3900,r4600,r4650,r4300,r5000"))
- 2 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3900,r4600,r4650,r5000"))
- 1 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300,r5000")))
- 7 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900,r5000")))
- 4 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
- 5 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 8 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3900,r6000,r4300,r5000")))
- 8 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900,r5000")))
- 5 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
- 6 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300,r5000")))
- 23 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900")))
- 12 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
- 15 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 32 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
- 21 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF")
- (eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300")))
- 36 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900")))
- 19 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
- 16 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
- 61 0)
-
- ;;; ??? Is this number right?
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
- 54 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 31 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
- 21 0)
-
- ;;; ??? Is this number right?
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
- 112 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
- 60 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
- 36 0)
-
- ;; R4300 FP instruction classes treated as part of the "imuldiv"
- ;; functional unit:
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
- 3 3)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fcmp,fabs,fneg,fmove") (eq_attr "cpu" "r4300"))
- 1 1)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
- 5 5)
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
- 8 8)
-
- (define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
- 29 29)
- (define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
- 58 58)
- \f
;; Include scheduling descriptions.
(include "3000.md")
(include "4130.md")
(include "5400.md")
(include "5500.md")
(include "7000.md")
(include "9000.md")
(include "sb1.md")
(include "sr71k.md")
\f
;;
;; ....................
--- 313,342 ----
(nil)
(nil)])
\f
! ;; These automota are used by generic.md and the processor-specific files
! ;; that override it.
! (define_automaton "alu,imuldiv")
! (define_cpu_unit "alu" "alu")
! (define_cpu_unit "imuldiv" "imuldiv")
;; Include scheduling descriptions.
(include "3000.md")
+ (include "4000.md")
+ (include "4100.md")
(include "4130.md")
+ (include "4300.md")
+ (include "4600.md")
+ (include "5000.md")
(include "5400.md")
(include "5500.md")
+ (include "6000.md")
(include "7000.md")
(include "9000.md")
(include "sb1.md")
(include "sr71k.md")
+ (include "generic.md")
\f
;;
;; ....................
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/4000.md Sat Jul 10 13:03:29 2004
***************
*** 0 ****
--- 1,33 ----
+ ;; R4000 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r4k_imul" 10
+ (and (eq_attr "cpu" "r4000")
+ (eq_attr "type" "imul,imadd"))
+ "imuldiv*10")
+
+ (define_insn_reservation "r4k_idiv" 69
+ (and (eq_attr "cpu" "r4000")
+ (eq_attr "type" "idiv"))
+ "imuldiv*69")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/4100.md Sat Jul 10 13:03:52 2004
***************
*** 0 ****
--- 1,52 ----
+ ;; VR4100 and VR4120 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r4100_load" 2
+ (and (eq_attr "cpu" "r4100,r4120")
+ (eq_attr "type" "load,fpload,fpidxload,xfer"))
+ "alu")
+
+ (define_insn_reservation "r4100_imul_si" 1
+ (and (eq_attr "cpu" "r4100,r4120")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "SI")))
+ "imuldiv")
+
+ (define_insn_reservation "r4100_imul_di" 4
+ (and (eq_attr "cpu" "r4100,r4120")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "DI")))
+ "imuldiv*4")
+
+ (define_insn_reservation "r4100_idiv_si" 35
+ (and (eq_attr "cpu" "r4100,r4120")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "imuldiv*35")
+
+ (define_insn_reservation "r4100_idiv_di" 67
+ (and (eq_attr "cpu" "r4100,r4120")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "imuldiv*67")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/4300.md Sat Jul 10 13:04:08 2004
***************
*** 0 ****
--- 1,86 ----
+ ;; VR4300 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r4300_load" 2
+ (and (eq_attr "cpu" "r4300")
+ (eq_attr "type" "load,fpload,fpidxload,xfer"))
+ "alu")
+
+ (define_insn_reservation "r4300_imul_si" 5
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "SI")))
+ "imuldiv*5")
+
+ (define_insn_reservation "r4300_imul_di" 8
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "DI")))
+ "imuldiv*8")
+
+ (define_insn_reservation "r4300_idiv_si" 37
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "imuldiv*37")
+
+ (define_insn_reservation "r4300_idiv_di" 69
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "imuldiv*69")
+
+ (define_insn_reservation "r4300_fmove" 1
+ (and (eq_attr "cpu" "r4300")
+ (eq_attr "type" "fcmp,fabs,fneg,fmove"))
+ "imuldiv")
+
+ (define_insn_reservation "r4300_fadd" 3
+ (and (eq_attr "cpu" "r4300")
+ (eq_attr "type" "fadd"))
+ "imuldiv*3")
+
+ (define_insn_reservation "r4300_fmul_single" 5
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "imuldiv*5")
+
+ (define_insn_reservation "r4300_fmul_double" 8
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "imuldiv*8")
+
+ (define_insn_reservation "r4300_fdiv_single" 29
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "SF")))
+ "imuldiv*29")
+
+ (define_insn_reservation "r4300_fdiv_double" 58
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "DF")))
+ "imuldiv*58")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/4600.md Sat Jul 10 13:05:32 2004
***************
*** 0 ****
--- 1,88 ----
+ ;; R4600 and R4650 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+ ;;
+ ;; We handle the R4600 and R4650 in much the same way. The only difference
+ ;; is in the integer multiplication and division costs.
+
+ (define_insn_reservation "r4600_imul" 10
+ (and (eq_attr "cpu" "r4600")
+ (eq_attr "type" "imul,imadd"))
+ "imuldiv*10")
+
+ (define_insn_reservation "r4600_idiv" 42
+ (and (eq_attr "cpu" "r4600")
+ (eq_attr "type" "idiv"))
+ "imuldiv*42")
+
+
+ (define_insn_reservation "r4650_imul" 4
+ (and (eq_attr "cpu" "r4650")
+ (eq_attr "type" "imul,imadd"))
+ "imuldiv*4")
+
+ (define_insn_reservation "r4650_idiv" 36
+ (and (eq_attr "cpu" "r4650")
+ (eq_attr "type" "idiv"))
+ "imuldiv*36")
+
+
+ (define_insn_reservation "r4600_load" 2
+ (and (eq_attr "cpu" "r4600,r4650")
+ (eq_attr "type" "load,fpload,fpidxload"))
+ "alu")
+
+ (define_insn_reservation "r4600_fmove" 1
+ (and (eq_attr "cpu" "r4600,r4650")
+ (eq_attr "type" "fabs,fneg,fmove"))
+ "alu")
+
+ (define_insn_reservation "r4600_fmul_single" 8
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r4600_fdiv_single" 32
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r4600_fdiv_double" 61
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF")))
+ "alu")
+
+ (define_insn_reservation "r4600_fsqrt_single" 31
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r4600_fsqrt_double" 60
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "DF")))
+ "alu")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/5000.md Sat Jul 10 13:14:39 2004
***************
*** 0 ****
--- 1,81 ----
+ ;; VR5000 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r5k_load" 2
+ (and (eq_attr "cpu" "r5000")
+ (eq_attr "type" "load,fpload,fpidxload,xfer"))
+ "alu")
+
+ (define_insn_reservation "r5k_imul_si" 5
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "SI")))
+ "imuldiv*5")
+
+ (define_insn_reservation "r5k_imul_di" 9
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "DI")))
+ "imuldiv*9")
+
+ (define_insn_reservation "r5k_idiv_si" 36
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "imuldiv*36")
+
+ (define_insn_reservation "r5k_idiv_di" 68
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "imuldiv*68")
+
+ (define_insn_reservation "r5k_fmove" 1
+ (and (eq_attr "cpu" "r5000")
+ (eq_attr "type" "fcmp,fabs,fneg,fmove"))
+ "alu")
+
+ (define_insn_reservation "r5k_fmul_single" 4
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r5k_fmul_double" 5
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "alu")
+
+ (define_insn_reservation "r5k_fdiv_single" 21
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r5k_fsqrt_double" 36
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "DF")))
+ "alu")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/6000.md Sat Jul 10 13:06:05 2004
***************
*** 0 ****
--- 1,57 ----
+ ;; R6000 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r6k_fcmp" 2
+ (and (eq_attr "cpu" "r6000")
+ (eq_attr "type" "fcmp"))
+ "alu")
+
+ (define_insn_reservation "r6k_fadd" 3
+ (and (eq_attr "cpu" "r6000")
+ (eq_attr "type" "fadd"))
+ "alu")
+
+ (define_insn_reservation "r6k_fmul_single" 5
+ (and (eq_attr "cpu" "r6000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r6k_fmul_double" 6
+ (and (eq_attr "cpu" "r6000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "alu")
+
+ (define_insn_reservation "r6k_fdiv_single" 15
+ (and (eq_attr "cpu" "r6000")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r6k_fdiv_double" 16
+ (and (eq_attr "cpu" "r6000")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF")))
+ "alu")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/generic.md Sat Jul 10 12:55:06 2004
***************
*** 0 ****
--- 1,102 ----
+ ;; Generic DFA-based pipeline description for MIPS targets
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file is derived from the old define_function_unit description.
+ ;; Each reservation can be overridden on a processor-by-processor basis.
+
+ (define_insn_reservation "generic_alu" 1
+ (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith,
+ shift,slt,clz,trap,multi,nop")
+ "alu")
+
+ (define_insn_reservation "generic_load" 3
+ (eq_attr "type" "load,fpload,fpidxload")
+ "alu")
+
+ (define_insn_reservation "generic_store" 1
+ (eq_attr "type" "store,fpstore,fpidxstore")
+ "alu")
+
+ (define_insn_reservation "generic_xfer" 2
+ (eq_attr "type" "xfer")
+ "alu")
+
+ (define_insn_reservation "generic_branch" 1
+ (eq_attr "type" "branch,jump,call")
+ "alu")
+
+ (define_insn_reservation "generic_hilo" 1
+ (eq_attr "type" "mfhilo,mthilo")
+ "imuldiv*3")
+
+ (define_insn_reservation "generic_imul" 17
+ (eq_attr "type" "imul,imadd")
+ "imuldiv*17")
+
+ (define_insn_reservation "generic_idiv" 38
+ (eq_attr "type" "idiv")
+ "imuldiv*38")
+
+ (define_insn_reservation "generic_fcvt" 1
+ (eq_attr "type" "fcvt")
+ "alu")
+
+ (define_insn_reservation "generic_fmove" 2
+ (eq_attr "type" "fabs,fneg,fmove")
+ "alu")
+
+ (define_insn_reservation "generic_fcmp" 3
+ (eq_attr "type" "fcmp")
+ "alu")
+
+ (define_insn_reservation "generic_fadd" 4
+ (eq_attr "type" "fadd")
+ "alu")
+
+ (define_insn_reservation "generic_fmul_single" 7
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF"))
+ "alu")
+
+ (define_insn_reservation "generic_fmul_double" 8
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF"))
+ "alu")
+
+ (define_insn_reservation "generic_fdiv_single" 23
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF"))
+ "alu")
+
+ (define_insn_reservation "generic_fdiv_double" 36
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF"))
+ "alu")
+
+ (define_insn_reservation "generic_fsqrt_single" 54
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "SF"))
+ "alu")
+
+ (define_insn_reservation "generic_fsqrt_double" 112
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "DF"))
+ "alu")
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Remove MIPS define_function_units
2004-07-10 16:09 ` Remove MIPS define_function_units Richard Sandiford
@ 2004-07-10 18:29 ` Eric Christopher
2004-07-12 7:07 ` Richard Sandiford
2004-07-10 18:31 ` Eric Christopher
1 sibling, 1 reply; 6+ messages in thread
From: Eric Christopher @ 2004-07-10 18:29 UTC (permalink / raw)
To: Richard Sandiford; +Cc: Paolo Bonzini, gcc-patches
> IMO, the downside of having to look in two places is far outweighed by
> the reduction in code duplication. Anyone who's actually interested in
> the performance of these processors would probably be better off
> starting from scratch anyway...
I agree.
> I'll run this through the usual bootstrap tests once the varargs stuff
> has finished. Eric, is the patch OK with you?
OK. Can you put a comment in mips.md where we include the scheduler
files about the possible duplicate locations?
Thanks.
-eric
--
Eric Christopher <echristo@redhat.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Remove MIPS define_function_units
2004-07-10 16:09 ` Remove MIPS define_function_units Richard Sandiford
2004-07-10 18:29 ` Eric Christopher
@ 2004-07-10 18:31 ` Eric Christopher
1 sibling, 0 replies; 6+ messages in thread
From: Eric Christopher @ 2004-07-10 18:31 UTC (permalink / raw)
To: Richard Sandiford; +Cc: Paolo Bonzini, gcc-patches
> IMO, the downside of having to look in two places is far outweighed by
> the reduction in code duplication. Anyone who's actually interested in
> the performance of these processors would probably be better off
> starting from scratch anyway...
I agree.
> I'll run this through the usual bootstrap tests once the varargs stuff
> has finished. Eric, is the patch OK with you?
OK. Can you put a comment in mips.md where we include the scheduler
files about the possible duplicate locations?
Thanks.
-eric
--
Eric Christopher <echristo@redhat.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Remove MIPS define_function_units
2004-07-10 18:29 ` Eric Christopher
@ 2004-07-12 7:07 ` Richard Sandiford
0 siblings, 0 replies; 6+ messages in thread
From: Richard Sandiford @ 2004-07-12 7:07 UTC (permalink / raw)
To: Eric Christopher; +Cc: Paolo Bonzini, gcc-patches
Eric Christopher <echristo@redhat.com> writes:
>> I'll run this through the usual bootstrap tests once the varargs stuff
>> has finished. Eric, is the patch OK with you?
>
> OK.
Thanks.
> Can you put a comment in mips.md where we include the scheduler
> files about the possible duplicate locations?
OK, here's what I added:
;; Pipeline descriptions.
;;
;; generic.md provides a fallback for processors without a specific
;; pipeline description. It is derived from the old define_function_unit
;; version and uses the "alu" and "imuldiv" units declared below.
;;
;; Some of the processor-specific files are also derived from old
;; define_function_unit descriptions and simply override the parts of
;; generic.md that don't apply. The other processor-specific files
;; are self-contained.
Bootstrapped & regression tested on mips64el-linux-gnu, applied to trunk.
Richard
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2004-07-12 5:24 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2004-07-10 12:40 [RFC] Automatically generated DFA descriptions Paolo Bonzini
2004-07-10 12:57 ` Richard Sandiford
2004-07-10 16:09 ` Remove MIPS define_function_units Richard Sandiford
2004-07-10 18:29 ` Eric Christopher
2004-07-12 7:07 ` Richard Sandiford
2004-07-10 18:31 ` Eric Christopher
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