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From: chenglulu <chenglulu@loongson.cn>
To: Xi Ruoyao <xry111@xry111.site>, gcc-patches@gcc.gnu.org
Cc: i@xen0n.name, xuchenghua@loongson.cn
Subject: Re: [PATCH v2 2/2] LoongArch: When the code model is extreme, the symbol address is obtained through macro instructions regardless of the value of -mexplicit-relocs.
Date: Mon, 22 Jan 2024 15:27:15 +0800	[thread overview]
Message-ID: <883986d4-e17b-6381-b3ec-75519859e7ea@loongson.cn> (raw)
In-Reply-To: <6078d647-4176-8aec-3384-d87c34464266@loongson.cn>


在 2024/1/19 下午4:51, chenglulu 写道:
>
> 在 2024/1/19 下午1:46, Xi Ruoyao 写道:
>> On Wed, 2024-01-17 at 17:57 +0800, chenglulu wrote:
>>>>> Virtual register 1479 will be used in insn 2744, but register 1479 
>>>>> was
>>>>> assigned the REG_UNUSED attribute in the previous instruction.
>>>>>
>>>>> The attached file is the wrong file.
>>>>> The compilation command is as follows:
>>>>>
>>>>> $ ./gcc/cc1 -fpreprocessed regrename.i -quiet -dp -dumpbase 
>>>>> regrename.c
>>>>> -dumpbase-ext .c -mno-relax -mabi=lp64d -march=loongarch64 -mfpu=64
>>>>> -msimd=lasx -mcmodel=extreme -mtune=loongarch64 -g3 -O2
>>>>> -Wno-int-conversion -Wno-implicit-int 
>>>>> -Wno-implicit-function-declaration
>>>>> -Wno-incompatible-pointer-types -version -o regrename.s
>>>>> -mexplicit-relocs=always -fdump-rtl-all-all
>>>> I've seen some "guality" test failures in GCC test suite as well.
>>>> Normally I just ignore the guality failures but this time they look 
>>>> very
>>>> suspicious.  I'll investigate these issues...
>>>>
>>> I've also seen this type of failed regression tests and I'll 
>>> continue to
>>> look at this issue as well.
>> The guality regression is simple: I didn't call
>> delegitimize_mem_from_attrs (the default TARGET_DELEGITIMIZE_ADDRESS) in
>> the custom implementation.
>>
>> The failure of this test case was because the compiler believes that two
>> (UNSPEC_PCREL_64_PART2 [(symbol)]) instances would always produce the
>> same result, but this isn't true because the result depends on PC.  Thus
>> (pc) needed to be included in the RTX, like:
>>
>>    [(set (match_operand:DI 0 "register_operand" "=r")
>>      (unspec:DI [(match_operand:DI 2 "") (pc)] 
>> UNSPEC_LA_PCREL_64_PART1))
>>     (set (match_operand:DI 1 "register_operand" "=r")
>>      (unspec:DI [(match_dup 2) (pc)] UNSPEC_LA_PCREL_64_PART2))]
>>
>> With this the buggy REG_UNUSED notes were gone.  But it then prevented
>> the CSE when loading the address of __tls_get_addr (i.e. if we address
>> 10 TLE_LD symbols in a function it would emit 10 instances of "la.global
>> __tls_get_addr") so I added an REG_EQUAL note for it.  For symbols other
>> than __tls_get_addr such notes are added automatically by optimization
>> passes.
>>
>> Updated patch attached.
>>
> I'm eliminating redundant la.global directives in my macro 
> implementation.
>
> I will be testing this patch.
>
>
>
>
With this patch, spec2006 can pass the test, but spec2017 621 and 654 
tests fail.
I haven't debugged the specific cause of the problem yet.


  reply	other threads:[~2024-01-22  7:27 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-05  3:40 [PATCH v2 0/2] When cmodel=extreme, add macro support and only support macros Lulu Cheng
2024-01-05  3:40 ` [PATCH v2 1/2] LoongArch: Add the macro implementation of mcmodel=extreme Lulu Cheng
2024-01-05  3:40 ` [PATCH v2 2/2] LoongArch: When the code model is extreme, the symbol address is obtained through macro instructions regardless of the value of -mexplicit-relocs Lulu Cheng
2024-01-05  8:37   ` Xi Ruoyao
2024-01-05  8:51     ` chenglulu
2024-01-05  9:57     ` chenglulu
2024-01-05 10:25       ` Xi Ruoyao
2024-01-05 11:55         ` Xi Ruoyao
2024-01-05 12:45           ` chenglulu
2024-01-05 14:16             ` Xi Ruoyao
2024-01-12  1:46               ` chenglulu
2024-01-12 11:42                 ` Xi Ruoyao
2024-01-13  7:01                   ` chenglulu
2024-01-13 13:05                     ` Xi Ruoyao
2024-01-13 14:05                       ` chenglulu
2024-01-17  9:38                       ` chenglulu
2024-01-17  9:50                         ` Xi Ruoyao
2024-01-17  9:57                           ` chenglulu
2024-01-19  5:46                             ` Xi Ruoyao
2024-01-19  8:51                               ` chenglulu
2024-01-22  7:27                                 ` chenglulu [this message]
2024-01-23 19:36                                   ` Xi Ruoyao
2024-01-25  0:48                                     ` chenglulu
2024-01-25  7:59                                       ` Xi Ruoyao

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