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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id d6-20020a17090a8d8600b0024e0141353dsm455612pjo.28.2023.05.15.21.16.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 May 2023 21:16:54 -0700 (PDT) Message-ID: <8865a17c-54ed-2c4c-cc5b-e3f3baf60a51@gmail.com> Date: Mon, 15 May 2023 22:16:53 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2 Content-Language: en-US To: Jin Ma , gcc-patches@gcc.gnu.org Cc: christoph.muellner@vrull.eu, kito.cheng@sifive.com, kito.cheng@gmail.com, palmer@dabbelt.com, ijinma@yeah.net References: <20230419095751.815-1-jinma@linux.alibaba.com> <20230515131628.953-1-jinma@linux.alibaba.com> From: Jeff Law In-Reply-To: <20230515131628.953-1-jinma@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_NUMSUBJECT,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 5/15/23 07:16, Jin Ma wrote: > This patch adds the 'Zfa' extension for riscv, which is based on: > https://github.com/riscv/riscv-isa-manual/commits/zfb > > The binutils-gdb for 'Zfa' extension: > https://sourceware.org/pipermail/binutils/2023-April/127060.html > > What needs special explanation is: > 1, The immediate number of the instructions FLI.H/S/D is represented in the assembly as a > floating-point value, with scientific counting when rs1 is 2,3, and decimal numbers for > the rest. > > Related llvm link: > https://reviews.llvm.org/D145645 > Related discussion link: > https://github.com/riscv/riscv-isa-manual/issues/980 > > 2, According to riscv-spec, "The FCVTMO D.W.D instruction was added principally to > accelerate the processing of JavaScript Numbers.", so it seems that no implementation > is required. > > 3, The instructions FMINM and FMAXM correspond to C23 library function fminimum and fmaximum. > Therefore, this patch has simply implemented the pattern of fminm3 and > fmaxm3 to prepare for later. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Add zfa extension version. > * config/riscv/constraints.md (zfli): Constrain the floating point number that the > instructions FLI.H/S/D can load. > * config/riscv/iterators.md (ceil): New. > (rup): New. > * config/riscv/riscv-opts.h (MASK_ZFA): New. > (TARGET_ZFA): New. > * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): New. > * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli): New. > (riscv_cannot_force_const_mem): If instruction FLI.H/S/D can be used, memory is not applicable. > (riscv_const_insns): Likewise. > (riscv_legitimize_const_move): Likewise. > (riscv_split_64bit_move_p): If instruction FLI.H/S/D can be used, no split is required. > (riscv_split_doubleword_move): Likewise. > (riscv_output_move): Output the mov instructions in zfa extension. > (riscv_print_operand): Output the floating-point value of the FLI.H/S/D immediate in assembly > (riscv_secondary_memory_needed): Likewise. > * config/riscv/riscv.md (fminm3): New. > (fmaxm3): New. > (movsidf2_low_rv32): New. > (movsidf2_high_rv32): New. > (movdfsisi3_rv32): New. > (f_quiet4_zfa): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zfa-fleq-fltq-rv32.c: New test. > * gcc.target/riscv/zfa-fleq-fltq.c: New test. > * gcc.target/riscv/zfa-fli-rv32.c: New test. > * gcc.target/riscv/zfa-fli-zfh-rv32.c: New test. > * gcc.target/riscv/zfa-fli-zfh.c: New test. > * gcc.target/riscv/zfa-fli.c: New test. > * gcc.target/riscv/zfa-fmovh-fmovp-rv32.c: New test. > * gcc.target/riscv/zfa-fround-rv32.c: New test. > * gcc.target/riscv/zfa-fround.c: New test. > --- > gcc/common/config/riscv/riscv-common.cc | 4 + > gcc/config/riscv/constraints.md | 21 +- > gcc/config/riscv/iterators.md | 5 + > gcc/config/riscv/riscv-opts.h | 3 + > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv.cc | 204 +++++++++++++++++- > gcc/config/riscv/riscv.md | 145 +++++++++++-- > .../gcc.target/riscv/zfa-fleq-fltq-rv32.c | 19 ++ > .../gcc.target/riscv/zfa-fleq-fltq.c | 19 ++ > gcc/testsuite/gcc.target/riscv/zfa-fli-rv32.c | 79 +++++++ > .../gcc.target/riscv/zfa-fli-zfh-rv32.c | 41 ++++ > gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c | 41 ++++ > gcc/testsuite/gcc.target/riscv/zfa-fli.c | 79 +++++++ > .../gcc.target/riscv/zfa-fmovh-fmovp-rv32.c | 10 + > .../gcc.target/riscv/zfa-fround-rv32.c | 42 ++++ > gcc/testsuite/gcc.target/riscv/zfa-fround.c | 42 ++++ > 16 files changed, 719 insertions(+), 36 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli.c > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround.c > > + > +/* Return index of the FLI instruction table if rtx X is an immediate constant that can > + be moved using a single FLI instruction in zfa extension. Return -1 if not found. */ > + > +int > +riscv_float_const_rtx_index_for_fli (rtx x) > +{ > + unsigned HOST_WIDE_INT *fli_value_array; > + > + machine_mode mode = GET_MODE (x); > + > + if (!TARGET_ZFA > + || !CONST_DOUBLE_P(x) > + || mode == VOIDmode > + || (mode == HFmode && !TARGET_ZFH) > + || (mode == SFmode && !TARGET_HARD_FLOAT) > + || (mode == DFmode && !TARGET_DOUBLE_FLOAT)) > + return -1; Do we also need to check Z[FDH]INX too? Otherwise it looks pretty good. We just need to wait for everything to freeze and finalization on the assembler interface. jeff