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[46.223.203.173]) by smtp.gmail.com with ESMTPSA id t26-20020a056402241a00b00543597cd190sm8187080eda.47.2023.11.09.07.21.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Nov 2023 07:21:02 -0800 (PST) Message-ID: <892a4082-f04a-4064-9e09-911da3cc4031@gmail.com> Date: Thu, 9 Nov 2023 16:21:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: rdapp.gcc@gmail.com Content-Language: en-US To: gcc-patches , palmer , Kito Cheng , jeffreyalaw , "juzhe.zhong@rivai.ai" From: Robin Dapp Subject: [PATCH] RISC-V/testsuite: Fix zvfh tests. Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, this fixes some zvfh test oversights as well as adds zfh to the target requirements. It's not strictly necessary to have zfh but it greatly simplifies test handling when we can just calculate the reference value instead of working around it. Regards Robin gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Adjust. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Ditto. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Ditto. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-1.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-2.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: New test. --- .../riscv/rvv/autovec/binop/fmax_zvfh-1.c | 11 ++--- .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c | 4 +- .../riscv/rvv/autovec/binop/fmin_zvfh-1.c | 1 - .../autovec/cond/cond_convert_float2int-1.h | 8 ---- .../autovec/cond/cond_convert_float2int-2.h | 8 ---- .../cond/cond_convert_float2int-rv32-1.c | 13 +++--- .../cond/cond_convert_float2int-rv32-2.c | 13 +++--- .../cond/cond_convert_float2int-rv64-1.c | 13 +++--- .../cond/cond_convert_float2int-rv64-2.c | 13 +++--- .../cond/cond_convert_float2int_run-1.c | 11 +++-- .../cond/cond_convert_float2int_run-2.c | 2 +- .../cond/cond_convert_float2int_zvfh-1.h | 35 ++++++++++++++ .../cond/cond_convert_float2int_zvfh-2.h | 34 ++++++++++++++ .../cond/cond_convert_float2int_zvfh-rv32-1.c | 17 +++++++ .../cond/cond_convert_float2int_zvfh-rv32-2.c | 17 +++++++ .../cond/cond_convert_float2int_zvfh-rv64-1.c | 17 +++++++ .../cond/cond_convert_float2int_zvfh-rv64-2.c | 17 +++++++ .../cond/cond_convert_float2int_zvfh_run-1.c | 35 ++++++++++++++ .../cond/cond_convert_float2int_zvfh_run-2.c | 31 +++++++++++++ .../cond/cond_convert_int2float_run-1.c | 11 +++-- .../cond/cond_convert_int2float_run-2.c | 11 +++-- .../rvv/autovec/cond/cond_fmax_zvfh_run-1.c | 4 +- .../rvv/autovec/cond/cond_fmax_zvfh_run-2.c | 2 +- .../rvv/autovec/cond/cond_fmax_zvfh_run-3.c | 2 +- .../rvv/autovec/cond/cond_fmax_zvfh_run-4.c | 2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-1.c | 2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-2.c | 2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-3.c | 2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-4.c | 2 +- .../rvv/autovec/cond/cond_sqrt_run-zvfh-1.c | 12 +++-- .../rvv/autovec/cond/cond_sqrt_run-zvfh-2.c | 11 +++-- .../riscv/rvv/autovec/reduc/reduc_zvfh-10.c | 7 ++- .../rvv/autovec/reduc/reduc_zvfh_run-10.c | 46 +++++++++---------- 33 files changed, 309 insertions(+), 107 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c index c137955619f..7e04cbff1e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c @@ -1,5 +1,5 @@ -/* { dg-do run { target { riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ #include @@ -7,16 +7,15 @@ #define FN(X) __builtin_fmax##X #endif -#define DEF_LOOP(FN, SUFFIX, TYPE) \ +#define DEF_LOOP(FN, SUFFIX, TYPE) \ void __attribute__ ((noipa)) \ test_##TYPE (TYPE *__restrict x, TYPE *__restrict y, int n) \ { \ for (int i = 0; i < n; ++i) \ - x[i] = FN (SUFFIX) (x[i], y[i]); \ + x[i] = FN (SUFFIX) (x[i], y[i]); \ } -#define TEST_ALL(T) \ - T (FN, f16, _Float16) \ +#define TEST_ALL(T) T (FN, f16, _Float16) TEST_ALL (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c index 4a248c28e0a..f8c39e39fa5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */ #include @@ -30,7 +30,7 @@ dst[7] = nan ("0.0"); \ dst[8] = INFINITY; \ dst[9] = -INFINITY; \ - kest_##TYPE (dst, y, N); \ + test_##TYPE (dst, y, N); \ for (int i = 0; i < N; ++i) \ { \ double ref = FN (SUFFIX) (x[i], y[i]); \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c index 39643a71f25..c7865be19ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c @@ -7,4 +7,3 @@ #include "fmax_zvfh-1.c" /* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+} 1 } } */ - diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h index 639adc34c3d..0c25fcdb36f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h @@ -15,8 +15,6 @@ /* FP -> INT */ #define TEST_ALL_F2X_SAME(T) \ - T (_Float16, uint16_t) \ - T (_Float16, int16_t) \ T (float, uint32_t) \ T (float, int32_t) \ T (double, uint64_t) \ @@ -24,17 +22,11 @@ /* FP -> wider-INT */ #define TEST_ALL_F2X_WIDER(T) \ - T (_Float16, uint32_t) \ - T (_Float16, int32_t) \ - T (_Float16, uint64_t) \ - T (_Float16, int64_t) \ T (float, uint64_t) \ T (float, int64_t) /* FP -> narrower-INT */ #define TEST_ALL_F2X_NARROWER(T) \ - T (_Float16, uint8_t) \ - T (_Float16, int8_t) \ T (float, uint8_t) \ T (float, int8_t) \ T (float, uint16_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h index 3d518a45cd2..7f2de38efe3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h @@ -14,8 +14,6 @@ /* FP -> INT */ #define TEST_ALL_F2X_SAME(T) \ - T (_Float16, uint16_t) \ - T (_Float16, int16_t) \ T (float, uint32_t) \ T (float, int32_t) \ T (double, uint64_t) \ @@ -23,17 +21,11 @@ /* FP -> wider-INT */ #define TEST_ALL_F2X_WIDER(T) \ - T (_Float16, uint32_t) \ - T (_Float16, int32_t) \ - T (_Float16, uint64_t) \ - T (_Float16, int64_t) \ T (float, uint64_t) \ T (float, int64_t) /* FP -> narrower-INT */ #define TEST_ALL_F2X_NARROWER(T) \ - T (_Float16, uint8_t) \ - T (_Float16, int8_t) \ T (float, uint8_t) \ T (float, int8_t) \ T (float, uint16_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c index 8cc0170edeb..b7400018fb4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c @@ -3,15 +3,14 @@ #include "cond_convert_float2int-1.h" -/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ -/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */ /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c index 44e990133ec..3bc1a4e2eeb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c @@ -3,15 +3,14 @@ #include "cond_convert_float2int-2.h" -/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ -/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */ /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c index 143e78c87d3..a65317c91cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c @@ -3,15 +3,14 @@ #include "cond_convert_float2int-1.h" -/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ -/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */ /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c index 2d85a48ab2a..b764b72a6b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c @@ -3,15 +3,14 @@ #include "cond_convert_float2int-2.h" -/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ -/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ -/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */ /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c index ed039a3066c..3f145475a0f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c @@ -11,15 +11,18 @@ OLD_TYPE a[N], pred[N]; \ for (int i = 0; i < N; ++i) \ { \ - a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + a[i] = (i & 1 ? i : 1.1 * i) * (i % 3 == 0 ? 1.2 : -1.5); \ b[i] = (i % 9) * (i % 7 + 1); \ pred[i] = (i % 7 < 4); \ - asm volatile("" ::: "memory"); \ + asm volatile ("" ::: "memory"); \ } \ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ for (int i = 0; i < N; ++i) \ - if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \ - __builtin_abort (); \ + { \ + NEW_TYPE ref = pred[i] ? a[i] : b[i]; \ + if (r[i] != ref) \ + __builtin_abort (); \ + } \ } int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c index 70271fdbb3c..a47602ad198 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c @@ -11,7 +11,7 @@ OLD_TYPE a[N], pred[N]; \ for (int i = 0; i < N; ++i) \ { \ - a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + a[i] = (i & 1 ? i : 1.2 * i) * (i % 3 == 0 ? 1 : -1); \ pred[i] = (i % 7 < 4); \ asm volatile("" ::: "memory"); \ } \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-1.h new file mode 100644 index 00000000000..3488b38e6bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-1.h @@ -0,0 +1,35 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, \ + NEW_TYPE *__restrict b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \ + } \ + } + +/* FP -> INT */ +#define TEST_ALL_F2X_SAME(T) \ + T (_Float16, uint16_t) \ + T (_Float16, int16_t) \ + +/* FP -> wider-INT */ +#define TEST_ALL_F2X_WIDER(T) \ + T (_Float16, uint32_t) \ + T (_Float16, int32_t) \ + T (_Float16, uint64_t) \ + T (_Float16, int64_t) \ + +/* FP -> narrower-INT */ +#define TEST_ALL_F2X_NARROWER(T) \ + T (_Float16, uint8_t) \ + T (_Float16, int8_t) \ + +TEST_ALL_F2X_SAME (DEF_LOOP) +TEST_ALL_F2X_WIDER (DEF_LOOP) +TEST_ALL_F2X_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-2.h new file mode 100644 index 00000000000..1e82d84884f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-2.h @@ -0,0 +1,34 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, NEW_TYPE b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \ + } \ + } + +/* FP -> INT */ +#define TEST_ALL_F2X_SAME(T) \ + T (_Float16, uint16_t) \ + T (_Float16, int16_t) \ + +/* FP -> wider-INT */ +#define TEST_ALL_F2X_WIDER(T) \ + T (_Float16, uint32_t) \ + T (_Float16, int32_t) \ + T (_Float16, uint64_t) \ + T (_Float16, int64_t) \ + +/* FP -> narrower-INT */ +#define TEST_ALL_F2X_NARROWER(T) \ + T (_Float16, uint8_t) \ + T (_Float16, int8_t) \ + +TEST_ALL_F2X_SAME (DEF_LOOP) +TEST_ALL_F2X_WIDER (DEF_LOOP) +TEST_ALL_F2X_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c new file mode 100644 index 00000000000..c13f1348370 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2int_zvfh-1.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ +/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c new file mode 100644 index 00000000000..ebb0a595425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2int_zvfh-2.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ +/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c new file mode 100644 index 00000000000..2405c7ff1e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2int_zvfh-1.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ +/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c new file mode 100644 index 00000000000..3b2455cb8ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_convert_float2int_zvfh-2.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ +/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c new file mode 100644 index 00000000000..00f01cadeb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_float2int_zvfh-1.h" + +#define N 77 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b[N]; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 1.1 * i) * (i % 3 == 0 ? 1.2 : -1.5); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + { \ + NEW_TYPE ref = pred[i] ? a[i] : b[i]; \ + if (r[i] != ref) \ + __builtin_abort (); \ + } \ + } + +int +main () +{ + TEST_ALL_F2X_SAME (TEST_LOOP) + TEST_ALL_F2X_WIDER (TEST_LOOP) + TEST_ALL_F2X_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c new file mode 100644 index 00000000000..c3dc653d783 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_float2int_zvfh-2.h" + +#define N 77 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b = 192; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 1.2 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_F2X_SAME (TEST_LOOP) + TEST_ALL_F2X_WIDER (TEST_LOOP) + TEST_ALL_F2X_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c index acb6716221f..cb7f35d5523 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c @@ -5,6 +5,8 @@ #define N 99 +#define EPS 1e-8 + #define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ { \ NEW_TYPE r[N], b[N]; \ @@ -14,12 +16,15 @@ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ b[i] = (i % 9) * (i % 7 + 1); \ pred[i] = (i % 7 < 4); \ - asm volatile("" ::: "memory"); \ + asm volatile ("" ::: "memory"); \ } \ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ for (int i = 0; i < N; ++i) \ - if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \ - __builtin_abort (); \ + { \ + NEW_TYPE ref = pred[i] ? a[i] : b[i]; \ + if (__builtin_fabsf (r[i] - ref) > EPS) \ + __builtin_abort (); \ + } \ } int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c index a4cf1ac8b8d..1ec6c591a81 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c @@ -5,6 +5,8 @@ #define N 99 +#define EPS 1e-8 + #define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ { \ NEW_TYPE r[N], b = 192.12; \ @@ -13,12 +15,15 @@ { \ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ pred[i] = (i % 7 < 4); \ - asm volatile("" ::: "memory"); \ + asm volatile ("" ::: "memory"); \ } \ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ for (int i = 0; i < N; ++i) \ - if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \ - __builtin_abort (); \ + { \ + NEW_TYPE ref = pred[i] ? a[i] : b; \ + if (__builtin_fabsf (r[i] - ref) > EPS) \ + __builtin_abort (); \ + } \ } int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c index 1609d2ced7b..ae6381ab07b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax_zvfh-1.c" @@ -18,7 +18,7 @@ test_##TYPE##_##NAME (x, y, pred, N); \ for (int i = 0; i < N; ++i) \ { \ - TYPE expected = i % 3 != 1 ? FN (y[i], CONST) : y[i]; \ + TYPE expected = i % 3 != 1 ? FN (y[i], CONST) : y[i]; \ if (x[i] != expected) \ __builtin_abort (); \ asm volatile ("" ::: "memory"); \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c index 6c33858cc40..697abb2b599 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax_zvfh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c index 6df48c220f3..d4ee99f2925 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax_zvfh-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c index 9bb1beb1418..c006c64f51e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax_zvfh-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c index b334f4d6bea..01a7dfdeb36 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c index 873f413c6b7..c2d693e15a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c index 94be087fb6e..4c4696851e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c index 8a144e85afa..49a0c671e8a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c index c96a1a6b099..e80ac755a92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c @@ -2,10 +2,11 @@ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */ #include "cond_sqrt-zvfh-1.c" -#include #define N 99 +#define EPS 1e-2 + #define TEST_LOOP(TYPE, OP) \ { \ TYPE r[N], a[N], pred[N]; \ @@ -13,12 +14,15 @@ { \ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : 2); \ pred[i] = (i % 7 < 4); \ - asm volatile("" ::: "memory"); \ + asm volatile ("" ::: "memory"); \ } \ test_##TYPE##_##OP (r, a, pred, N); \ for (int i = 0; i < N; ++i) \ - if (r[i] != (pred[i] ? OP (a[i]) : a[i])) \ - __builtin_abort (); \ + { \ + float ref = pred[i] ? __builtin_sqrtf (a[i]) : a[i]; \ + if (__builtin_fabsf (r[i] - ref) > EPS) \ + __builtin_abort (); \ + } \ } int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c index 3386242bdad..6f437b63468 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c @@ -5,6 +5,8 @@ #define N 99 +#define EPS 1e-2 + #define TEST_LOOP(TYPE, OP) \ { \ TYPE r[N], a[N], b[N], pred[N]; \ @@ -13,12 +15,15 @@ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : 2); \ b[i] = (i % 9) * (i % 7 + 1); \ pred[i] = (i % 7 < 4); \ - asm volatile("" ::: "memory"); \ + asm volatile ("" ::: "memory"); \ } \ test_##TYPE##_##OP (r, a, b, pred, N); \ for (int i = 0; i < N; ++i) \ - if (r[i] != (pred[i] ? OP (a[i]) : b[i])) \ - __builtin_abort (); \ + { \ + float ref = pred[i] ? __builtin_sqrtf (a[i]) : b[i]; \ + if (__builtin_fabsf (r[i] - ref) > EPS) \ + __builtin_abort (); \ + } \ } int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c index 0651e3177b7..b3bba249c04 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c @@ -7,16 +7,15 @@ TYPE __attribute__ ((noinline, noclone)) \ reduc_##NAME##_##TYPE (TYPE *a, int n) \ { \ - TYPE r = -0.0; \ + TYPE r = -0.0; \ for (int i = 0; i < n; ++i) \ r = MAXMIN_OP (r, a[i]); \ return r; \ } #define TEST_FMAXMIN(T) \ - T (_Float16, max, __builtin_fmaxf16) \ - T (_Float16, min, __builtin_fminf16) \ - + T (_Float16, max, __builtin_fmaxf16) \ + T (_Float16, min, __builtin_fminf16) TEST_FMAXMIN (DEF_REDUC_FMAXMIN) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c index 2b8bcdfe8fa..ab047d7077d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */ #include @@ -7,29 +7,29 @@ #define NUM_ELEMS(TYPE) (73 + sizeof (TYPE)) -#define INIT_VECTOR(TYPE) \ - TYPE a[NUM_ELEMS (TYPE) + 1]; \ - for (int i = 0; i < NUM_ELEMS (TYPE) + 1; i++) \ - { \ - a[i] = ((i * 2) * (i & 1 ? 1 : -1) | 3); \ - asm volatile ("" ::: "memory"); \ - } \ - a[0] = -0.0; \ - a[1] = nan ("0.0"); \ - a[2] = nan ("1.0"); \ - a[3] = 0.0; \ - a[4] = -INFINITY; \ - a[5] = INFINITY; \ +#define INIT_VECTOR(TYPE) \ + TYPE a[NUM_ELEMS (TYPE) + 1]; \ + for (int i = 0; i < NUM_ELEMS (TYPE) + 1; i++) \ + { \ + a[i] = ((i * 2) * (i & 1 ? 1 : -1) | 3); \ + asm volatile ("" ::: "memory"); \ + } \ + a[0] = -0.0; \ + a[1] = nan ("0.0"); \ + a[2] = nan ("1.0"); \ + a[3] = 0.0; \ + a[4] = -INFINITY; \ + a[5] = INFINITY;\ -#define TEST_REDUC_FMAXMIN(TYPE, NAME, MAXMIN_OP) \ - { \ - INIT_VECTOR (TYPE); \ - TYPE r1 = reduc_##NAME##_##TYPE (a, NUM_ELEMS (TYPE)); \ - volatile TYPE r2 = -0.0; \ - for (int i = 0; i < NUM_ELEMS (TYPE); ++i) \ - r2 = MAXMIN_OP (r2, a[i]); \ - if (r1 != r2) \ - __builtin_abort (); \ +#define TEST_REDUC_FMAXMIN(TYPE, NAME, MAXMIN_OP) \ + { \ + INIT_VECTOR (TYPE); \ + TYPE r1 = reduc_##NAME##_##TYPE (a, NUM_ELEMS (TYPE)); \ + volatile TYPE r2 = -0.0; \ + for (int i = 0; i < NUM_ELEMS (TYPE); ++i) \ + r2 = MAXMIN_OP (r2, a[i]); \ + if (r1 != r2) \ + __builtin_abort (); \ } __attribute__ ((optimize ("1"))) -- 2.41.0