backport the fixes of PR target/64011 and /61749 to 4.9 gcc

[weixiangyu <weixiangyu@huawei.com>]

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Hi,
The first patch backports the fix of PR target/64011(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64011) to the 4.9 branch from trunk r219717,
and the second patch backports the fix of PR target/61749(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61749) to the 4.9 branch from trunk r215046.

Here comes the first patch:
===================================================================
--- gcc/ChangeLog-HCC   (revision 130394)
+++ gcc/ChangeLog-HCC   (working copy)
@@ -1,3 +1,12 @@
+2015-05-25 y00166676  <felix.yang@huawei.com>
+
+       Backport from trunk r219717.
+       2015-01-15  Jiong Wang  <jiong.wang@arm.com>
+
+       PR rtl-optimization/64011
+       * expmed.c (store_bit_field_using_insv): Warn and truncate bitsize when
+       there is partial overflow.


And the second one:  
===================================================================
--- gcc/ChangeLog-HCC   (revision 130589)
+++ gcc/ChangeLog-HCC   (revision 130590)
@@ -1,3 +1,29 @@
+2015-05-26 y00166676  <felix.yang@huawei.com>
+
+       Backport from trunk r215046.
+       2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/61749
+       * config/aarch64/aarch64-builtins.c (aarch64_types_quadop_qualifiers):
+       Use qualifier_immediate for last operand.  Rename to...
+       (aarch64_types_ternop_lane_qualifiers): ... This.
+       (TYPES_QUADOP): Rename to...
+       (TYPES_TERNOP_LANE): ... This.
+       (aarch64_simd_expand_args): Return const0_rtx when encountering user
+       error.  Change return of 0 to return of NULL_RTX.
+       (aarch64_crc32_expand_builtin): Likewise.
+       (aarch64_expand_builtin): Return NULL_RTX instead of 0.
+       ICE when expanding unknown builtin.
+       * config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use
+       TERNOP_LANE qualifiers.
+       (sqdmlsl_lane): Likewise.
+       (sqdmlal_laneq): Likewise.
+       (sqdmlsl_laneq): Likewise.
+       (sqdmlal2_lane): Likewise.
+       (sqdmlsl2_lane): Likewise.
+       (sqdmlal2_laneq): Likewise.
+       (sqdmlsl2_laneq): Likewise.
+
* gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test.

Thanks for your attention,
Xiangyu Wei

[-- Attachment #2: pr64011-backport-4.9.diff --]
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Index: gcc/ChangeLog-HCC
===================================================================
--- gcc/ChangeLog-HCC   (revision 130410)
+++ gcc/ChangeLog-HCC   (revision 130411)
@@ -1,3 +1,12 @@
+2015-05-25 y00166676  <felix.yang@huawei.com>
+
+       Backport from trunk r219717.
+       2015-01-15  Jiong Wang  <jiong.wang@arm.com>
+
+       PR rtl-optimization/64011
+       * expmed.c (store_bit_field_using_insv): Warn and truncate bitsize when
+       there is partial overflow. 
+
 2015-05-21 y00166676  <felix.yang@huawei.com>
 
        [TASK] Merge bugfix from GCC 4.9 branch.
Index: gcc/expmed.c
===================================================================
--- gcc/expmed.c        (revision 130410)
+++ gcc/expmed.c        (revision 130411)
@@ -540,6 +540,21 @@
       copy_back = true;
     }
 
+  /* There are similar overflow check at the start of store_bit_field_1,
+     but that only check the situation where the field lies completely
+     outside the register, while there do have situation where the field
+     lies partialy in the register, we need to adjust bitsize for this
+     partial overflow situation.  Without this fix, pr48335-2.c on big-endian
+     will broken on those arch support bit insert instruction, like arm, aarch64
+     etc.  */
+  if (bitsize + bitnum > unit && bitnum < unit)
+    {
+      warning (OPT_Wextra, "write of %wu-bit data outside the bound of "
+              "destination object, data truncated into %wu-bit",
+              bitsize, unit - bitnum);
+      bitsize = unit - bitnum;
+    }
+
   /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
      "backwards" from the size of the unit we are inserting into.
      Otherwise, we count bits from the most significant on a

[-- Attachment #3: pr61749-backport-4.9.diff --]
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Index: gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c      (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c      (revision 130590)
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+
+#include "arm_neon.h"
+
+int32x4_t
+foo (int32x4_t a, int16x4_t b, int16x4_t c, int d)
+{
+  return vqdmlal_lane_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo1 (int32x4_t a, int16x4_t b, int16x8_t c, int d)
+{
+  return vqdmlal_laneq_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo2 (int32x4_t a, int16x4_t b, int16x4_t c, int d)
+{
+  return vqdmlsl_lane_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo3 (int32x4_t a, int16x4_t b, int16x8_t c, int d)
+{
+  return vqdmlsl_laneq_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo4 (int32x4_t a, int16x8_t b, int16x4_t c, int d)
+{
+  return vqdmlal_high_lane_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo5 (int32x4_t a, int16x8_t b, int16x4_t c, int d)
+{
+  return vqdmlsl_high_lane_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo6 (int32x4_t a, int16x8_t b, int16x8_t c, int d)
+{
+  return vqdmlal_high_laneq_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo7 (int32x4_t a, int16x8_t b, int16x8_t c, int d)
+{
+  return vqdmlsl_high_laneq_s16 (a, b, c, d);
+}
+
+
+/* { dg-excess-errors "incompatible type for argument" } */

Property changes on: gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c
___________________________________________________________________
Added: svn:executable
   + *

Index: gcc/testsuite/ChangeLog-HCC
===================================================================
--- gcc/testsuite/ChangeLog-HCC (revision 130589)
+++ gcc/testsuite/ChangeLog-HCC (revision 130590)
@@ -1,3 +1,11 @@
+2015-05-26  Felix Yang  <felix.yang@huawei.com>
+
+       Backport from trunk r215046.
+       2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/61749
+       * gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test.
+
 2015-01-19  Jiong Wang  <jiong.wang@arm.com>
 
        * gcc.target/aarch64/pr64304.c: New testcase.
Index: gcc/config/aarch64/aarch64-builtins.c
===================================================================
--- gcc/config/aarch64/aarch64-builtins.c       (revision 130589)
+++ gcc/config/aarch64/aarch64-builtins.c       (revision 130590)
@@ -172,10 +172,10 @@
 #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers)
 
 static enum aarch64_type_qualifiers
-aarch64_types_quadop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_none,
-      qualifier_none, qualifier_none };
-#define TYPES_QUADOP (aarch64_types_quadop_qualifiers)
+      qualifier_none, qualifier_immediate };
+#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers)
 
 static enum aarch64_type_qualifiers
 aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
@@ -818,8 +818,11 @@
            case SIMD_ARG_CONSTANT:
              if (!(*insn_data[icode].operand[argc + have_retval].predicate)
                  (op[argc], mode[argc]))
-               error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
+               {
+                 error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
                       "expected %<const int%>", argc + 1);
+                 return const0_rtx;
+               }
              break;
 
            case SIMD_ARG_STOP:
@@ -886,7 +889,7 @@
       }
 
   if (!pat)
-    return 0;
+    return NULL_RTX;
 
   emit_insn (pat);
 
@@ -968,7 +971,7 @@
   if (fcode >= AARCH64_SIMD_BUILTIN_BASE)
     return aarch64_simd_expand_builtin (fcode, exp, target);
 
-  return NULL_RTX;
+  gcc_unreachable ();
 }
 
 tree
Index: gcc/config/aarch64/aarch64-simd-builtins.def
===================================================================
--- gcc/config/aarch64/aarch64-simd-builtins.def        (revision 130589)
+++ gcc/config/aarch64/aarch64-simd-builtins.def        (revision 130590)
@@ -145,16 +145,16 @@
   BUILTIN_VSDQ_I_BHSI (UNOP, sqabs, 0)
   BUILTIN_VSDQ_I_BHSI (UNOP, sqneg, 0)
 
-  BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
-  BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
-  BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
-  BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_lane, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_lane, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_laneq, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_laneq, 0)
   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
-  BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
-  BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
-  BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
-  BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_lane, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_lane, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_laneq, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_laneq, 0)
   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
Index: gcc/ChangeLog-HCC
===================================================================
--- gcc/ChangeLog-HCC   (revision 130589)
+++ gcc/ChangeLog-HCC   (revision 130590)
@@ -1,3 +1,29 @@
+2015-05-26 y00166676  <felix.yang@huawei.com>
+
+       Backport from trunk r215046.
+       2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/61749
+       * config/aarch64/aarch64-builtins.c (aarch64_types_quadop_qualifiers):
+       Use qualifier_immediate for last operand.  Rename to...
+       (aarch64_types_ternop_lane_qualifiers): ... This.
+       (TYPES_QUADOP): Rename to...
+       (TYPES_TERNOP_LANE): ... This.
+       (aarch64_simd_expand_args): Return const0_rtx when encountering user
+       error.  Change return of 0 to return of NULL_RTX.
+       (aarch64_crc32_expand_builtin): Likewise.
+       (aarch64_expand_builtin): Return NULL_RTX instead of 0.
+       ICE when expanding unknown builtin.
+       * config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use
+       TERNOP_LANE qualifiers.
+       (sqdmlsl_lane): Likewise.
+       (sqdmlal_laneq): Likewise.
+       (sqdmlsl_laneq): Likewise.
+       (sqdmlal2_lane): Likewise.
+       (sqdmlsl2_lane): Likewise.
+       (sqdmlal2_laneq): Likewise.
+       (sqdmlsl2_laneq): Likewise.
+
 2015-05-25 y00166676  <felix.yang@huawei.com>
 
        Backport from trunk r219717.