* [PATCH] Fix typo in chapter level for RISC-V attributes
@ 2022-09-23 18:43 Torbjörn SVENSSON
2022-09-24 18:34 ` Jeff Law
0 siblings, 1 reply; 2+ messages in thread
From: Torbjörn SVENSSON @ 2022-09-23 18:43 UTC (permalink / raw)
To: gcc-patches; +Cc: Torbjörn SVENSSON
The "RISC-V specific attributes" section should be at the same level
as "PowerPC-specific attributes".
gcc/ChangeLog:
* doc/sourcebuild.texi: Fix chapter level.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
---
gcc/doc/sourcebuild.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 760ff9559a6..52357cc7aee 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2447,7 +2447,7 @@ PowerPC target pre-defines macro _ARCH_PWR9 which means the @code{-mcpu}
setting is Power9 or later.
@end table
-@subsection RISC-V specific attributes
+@subsubsection RISC-V specific attributes
@table @code
--
2.25.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] Fix typo in chapter level for RISC-V attributes
2022-09-23 18:43 [PATCH] Fix typo in chapter level for RISC-V attributes Torbjörn SVENSSON
@ 2022-09-24 18:34 ` Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2022-09-24 18:34 UTC (permalink / raw)
To: gcc-patches
On 9/23/22 12:43, Torbjörn SVENSSON via Gcc-patches wrote:
> The "RISC-V specific attributes" section should be at the same level
> as "PowerPC-specific attributes".
>
> gcc/ChangeLog:
>
> * doc/sourcebuild.texi: Fix chapter level.
OK
jeff
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