From: "Lehua Ding" <lehua.ding@rivai.ai>
To: "Kito Cheng" <kito.cheng@gmail.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>,
"juzhe.zhong" <juzhe.zhong@rivai.ai>,
"rdapp.gcc" <rdapp.gcc@gmail.com>, palmer <palmer@rivosinc.com>,
jeffreyalaw <jeffreyalaw@gmail.com>
Subject: Re: [PATCH 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
Date: Thu, 10 Aug 2023 15:08:10 +0800 [thread overview]
Message-ID: <8F002E7E84D3076C+tencent_2BF58BBBC29CED76651F12D7EA33EEC80908@qq.com> (raw)
In-Reply-To: <CA+yXCZCGPP8aUH-ZA9k9kMc0q==cqPRYgG5PAUVO6sAAVj1bWg@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1993 bytes --]
Thanks so much for Kito's online and offline comments.
I have upload V2 patchs which address all comments.
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626935.html
Best,
Lehua
------------------ Original ------------------
From: "Kito Cheng" <kito.cheng@gmail.com>;
Date: Mon, Aug 7, 2023 04:51 PM
To: "Lehua Ding"<lehua.ding@rivai.ai>;
Cc: "gcc-patches"<gcc-patches@gcc.gnu.org>;"juzhe.zhong"<juzhe.zhong@rivai.ai>;"rdapp.gcc"<rdapp.gcc@gmail.com>;"palmer"<palmer@rivosinc.com>;"jeffreyalaw"<jeffreyalaw@gmail.com>;
Subject: Re: [PATCH 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
Thanks for the high quality patch, it's generally LGTM, only a few
minor comments :)
> + /* The number and alignment of vector registers need for this scalable vector
> + argument. When the mode size is less than a full vector, we use 1 vector
> + register to pass. Just call TARGET_HARD_REGNO_NREGS for the number
> + infomation. */
gmail told me here is a typo: information :P
> + int nregs = riscv_hard_regno_nregs (V_ARG_FIRST, mode);
> + int LMUL = riscv_v_ext_tuple_mode_p (mode)
> + ? nregs / riscv_vector::get_nf (mode)
> + : nregs;
> + int arg_reg_start = V_ARG_FIRST - V_REG_FIRST;
> + int arg_reg_end = V_ARG_LAST - V_REG_FIRST;
> + int aligned_reg_start = (arg_reg_start + LMUL - 1) & -LMUL;
Use` ROUND_UP (arg_reg_start, LMUL)`
next prev parent reply other threads:[~2023-08-10 7:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 9:01 [PATCH 0/3] RISC-V: Add an experimental vector calling convention Lehua Ding
2023-07-20 9:01 ` [PATCH 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns Lehua Ding
2023-08-07 8:51 ` Kito Cheng
2023-08-10 7:08 ` Lehua Ding [this message]
2023-07-20 9:01 ` [PATCH 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed Lehua Ding
2023-08-07 6:53 ` Kito Cheng
2023-07-20 9:01 ` [PATCH 3/3] RISC-V: Part-3: Output .variant_cc directive for vector function Lehua Ding
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