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([2601:681:8600:13d0::99f]) by smtp.gmail.com with ESMTPSA id i64-20020a628743000000b0063b89da3adcsm3399946pfe.12.2023.04.21.12.32.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Apr 2023 12:32:01 -0700 (PDT) Message-ID: <8a40f438-f5fc-d417-fb61-8de9a34b8ae9@gmail.com> Date: Fri, 21 Apr 2023 13:31:59 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [RFC PATCH v1 05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez Content-Language: en-US To: Philipp Tomsich , gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> <20230210224150.2801962-6-philipp.tomsich@vrull.eu> From: Jeff Law In-Reply-To: <20230210224150.2801962-6-philipp.tomsich@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2/10/23 15:41, Philipp Tomsich wrote: > When if-conversion in noce_try_store_flag_mask starts the sequence off > with an order-operator, our patterns for czero.eqz/nez will receive > the result of the order-operator as a register argument; consequently, > they can't know that the result will be either 1 or 0. > > To convey this information (and make czero.eqz/nez applicable), we > wrap the result of the order-operator in a eq/ne against (const_int 0). > This commit adds the split pattern to handle these cases. > > During if-conversion, if noce_try_store_flag_mask succeeds, we may see > if (cur < next) { > next = 0; > } > transformed into > 27: r82:SI=ltu(r76:DI,r75:DI) > REG_DEAD r76:DI > 28: r81:SI=r82:SI^0x1 > REG_DEAD r82:SI > 29: r80:DI=zero_extend(r81:SI) > REG_DEAD r81:SI > > This currently escapes the combiner, as RISC-V does not have a pattern > to apply the 'slt' instruction to 'geu' verbs. By adding a pattern in > this commit, we match such cases. > > gcc/ChangeLog: > > * config/riscv/predicates.md (anyge_operator): Define. > (anygt_operator): Same. > (anyle_operator): Same. > (anylt_operator): Same. > * config/riscv/riscv.md: Helpers for ge(u) & le(u). > * config/riscv/zicond.md: Add split to wrap an an > order-operator suitably for generating czero.eqz/nez > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zicond-le-02.c: New test. > * gcc.target/riscv/zicond-lt-03.c: New test. Conceptually OK. As has been noted, we need to switch to the if-then_else form rather than (and (neg)). OK with that change. jeff