From: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>
To: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>
Subject: Re: [PATCH][ARM][GCC][3/x]: MVE ACLE intrinsics framework patch.
Date: Thu, 19 Dec 2019 17:50:00 -0000 [thread overview]
Message-ID: <8a77143e-dc33-9da4-9534-dd2082676395@foss.arm.com> (raw)
In-Reply-To: <DBBPR08MB4775E0A19EB73804879BBC009B710@DBBPR08MB4775.eurprd08.prod.outlook.com>
Hi Srinath,
On 11/14/19 7:12 PM, Srinath Parvathaneni wrote:
> Hello,
>
> This patch is part of MVE ACLE intrinsics framework.
>
> The patch supports the use of emulation for the double-precision
> arithmetic
> operations for MVE. This changes are to support the MVE ACLE
> intrinsics which
> operates on vector floating point arithmetic operations.
>
> Please refer to Arm reference manual [1] for more details.
> [1]
> https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.102521798.659307368.1572453718-1501600630.1548848914
>
> Regression tested on arm-none-eabi and found no regressions.
>
> Ok for trunk?
>
> Thanks,
> Srinath.
>
> gcc/ChangeLog:
>
> 2019-11-11Â Andre Vieira <andre.simoesdiasvieira@arm.com>
> Â Â Â Â Â Â Â Â Â Â Â Srinath Parvathaneni <srinath.parvathaneni@arm.com>
>
> Â Â Â Â Â Â Â * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify
> function to add
> Â Â Â Â Â Â Â emulator calls for dobule precision arithmetic operations for MVE.
I'm a bit confused by the changelog and the comment in the patch....
>
>
> ###############    Attachment also inlined for ease of reply  Â
> ###############
>
>
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index
> 6faed76206b93c1a9dea048e2f693dc16ee58072..358b2638b65a2007d1c7e8062844b67682597f45
> 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -5658,9 +5658,25 @@ arm_libcall_uses_aapcs_base (const_rtx libcall)
> Â Â Â Â Â Â /* Values from double-precision helper functions are returned
> in core
> Â Â Â Â Â Â Â Â Â registers if the selected core only supports single-precision
>          arithmetic, even if we are using the hard-float ABI. The
> same is
> -Â Â Â Â Â Â Â true for single-precision helpers, but we will never be using the
> -Â Â Â Â Â Â Â hard-float ABI on a CPU which doesn't support single-precision
> -       operations in hardware. */
> +Â Â Â Â Â Â Â true for single-precision helpers except in case of MVE,
> because in
> +Â Â Â Â Â Â Â MVE we will be using the hard-float ABI on a CPU which
> doesn't support
> +       single-precision operations in hardware. In MVE the
> following check
> +Â Â Â Â Â Â Â enables use of emulation for the double-precision arithmetic
> +       operations. */
> +Â Â Â Â Â if (TARGET_HAVE_MVE)
> +Â Â Â Â Â Â {
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (add_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (sdiv_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (smul_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (neg_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (sub_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (eq_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (lt_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (le_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (ge_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (gt_optab, SFmode));
> +Â Â Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (unord_optab, SFmode));
> +Â Â Â Â Â Â }
... this adds emulation for SFmode but you say you want double-precision
emulation?
Can you demonstrate what this patch wants to achieve with a testcase?
Thanks,
Kyrill
> Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (add_optab, DFmode));
> Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (sdiv_optab, DFmode));
> Â Â Â Â Â Â add_libcall (libcall_htab, optab_libfunc (smul_optab, DFmode));
>
next prev parent reply other threads:[~2019-12-19 17:40 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-14 19:34 [PATCH][ARM][GCC][0/x]: Support for MVE ACLE intrinsics Srinath Parvathaneni
2019-11-14 19:13 ` [PATCH][ARM][GCC][2/x]: MVE ACLE intrinsics framework patch Srinath Parvathaneni
2019-12-19 17:24 ` Kyrill Tkachov
2019-11-14 19:13 ` [PATCH][ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics Srinath Parvathaneni
2019-12-19 17:39 ` Kyrill Tkachov
2019-11-14 19:13 ` [PATCH][ARM][GCC][2/2x]: MVE intrinsics with binary operands Srinath Parvathaneni
2019-11-14 19:13 ` [PATCH][ARM][GCC][3/x]: MVE ACLE intrinsics framework patch Srinath Parvathaneni
2019-12-19 17:50 ` Kyrill Tkachov [this message]
2019-11-14 19:13 ` [PATCH][ARM][GCC][3/2x]: MVE intrinsics with binary operands Srinath Parvathaneni
2019-11-14 19:13 ` [PATCH][ARM][GCC][3/4x]: MVE intrinsics with quaternary operands Srinath Parvathaneni
2019-11-14 19:13 ` [PATCH][ARM][GCC][2/1x]: MVE intrinsics with unary operand Srinath Parvathaneni
2019-12-19 18:05 ` Kyrill Tkachov
2019-11-14 19:13 ` [PATCH][ARM][GCC][3/3x]: MVE intrinsics with ternary operands Srinath Parvathaneni
2019-11-14 19:13 ` [PATCH][ARM][GCC][5/2x]: MVE intrinsics with binary operands Srinath Parvathaneni
2019-11-14 19:13 ` [PATCH][ARM][GCC][3/1x]: MVE intrinsics with unary operand Srinath Parvathaneni
2019-11-14 19:14 ` [PATCH][ARM][GCC][1/4x]: MVE intrinsics with quaternary operands Srinath Parvathaneni
2019-11-14 19:14 ` [PATCH][ARM][GCC][1/2x]: MVE intrinsics with binary operands Srinath Parvathaneni
2019-12-19 19:10 ` Kyrill Tkachov
2019-11-14 19:15 ` [PATCH][ARM][GCC][2/4x]: MVE intrinsics with quaternary operands Srinath Parvathaneni
2019-11-14 19:15 ` [PATCH][ARM][GCC][7/5x]: MVE store intrinsics which stores byte,half word or word to memory Srinath Parvathaneni
2019-11-14 19:15 ` [PATCH][ARM][GCC][4/2x]: MVE intrinsics with binary operands Srinath Parvathaneni
2019-11-14 19:15 ` [PATCH][ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix Srinath Parvathaneni
2019-11-14 19:15 ` [PATCH][ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix Srinath Parvathaneni
2019-11-14 19:15 ` [PATCH][ARM][GCC][2/5x]: MVE load intrinsics Srinath Parvathaneni
2019-11-14 19:15 ` [PATCH][ARM][GCC][8/5x]: Remaining MVE store intrinsics which stores an half word, word and double word to memory Srinath Parvathaneni
2019-11-14 19:15 ` [PATCH][ARM][GCC][1/5x]: MVE store intrinsics Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][1/x]: MVE ACLE intrinsics framework patch Srinath Parvathaneni
2019-12-18 17:18 ` Kyrill Tkachov
2019-11-14 19:16 ` [PATCH][ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with unary operand Srinath Parvathaneni
2019-12-19 17:57 ` Kyrill Tkachov
2019-11-14 19:16 ` [PATCH][ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads half word and word or double word from memory Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byte, halfword, or word from memory Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][14x]: MVE ACLE whole vector left shift with carry intrinsics Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][13x]: MVE ACLE scalar shift intrinsics Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][2/8x]: MVE ACLE gather load and scatter store intrinsics with writeback Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][2/3x]: MVE intrinsics with ternary operands Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][11x]: MVE ACLE vector interleaving store and deinterleaving load intrinsics and also aliases to vstr and vldr intrinsics Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][4/4x]: MVE intrinsics with quaternary operands Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][4/1x]: MVE intrinsics with unary operand Srinath Parvathaneni
2019-12-19 18:16 ` Kyrill Tkachov
2019-11-14 19:16 ` [PATCH][ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup intrinsics with writeback Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across beats" and "beat-wise substract" Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic plus operator Srinath Parvathaneni
2019-11-14 19:16 ` [PATCH][ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-care) variant Srinath Parvathaneni
2019-11-14 19:27 ` [PATCH][ARM][GCC][1/3x]: MVE intrinsics with ternary operands Srinath Parvathaneni
2019-12-12 16:09 ` [PATCH][ARM][GCC][0/x]: Support for MVE ACLE intrinsics Kyrill Tkachov
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