[PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

[PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

[Thomas Preudhomme]

Hi,

This patch series adds support for the ARMv8-R architecture[1] and ARM 
Cortex-R52[2] to GCC. The patch series consist of the following patches:

[ 1/3] Add missing MIDR information for ARM Cortex-R7 and Cortex-R8 processor
[ 2/3] Add support for ARMv8-R architecture
[ 3/3] Add support for ARM Cortex-R52

[1] 
https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile
[2] https://developer.arm.com/products/processors/cortex-r/cortex-r52

[PATCH 1/3, GCC/ARM] Add MIDR info for ARM Cortex-R7 and Cortex-R8

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 450 bytes --]

Hi,

The driver is missing MIDR information for processors ARM Cortex-R7 and
Cortex-R8 to support -march/-mcpu/-mtune=native on the command line.
This patch adds the missing information.

ChangeLog entry is as follows:

*** gcc/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
	Cortex-R7 and Cortex-R8 processors.

Is this ok for master?

Best regards,

Thomas

[-- Attachment #2: 1_add_cortex_r7_r8_midr.patch --]
[-- Type: text/x-patch, Size: 623 bytes --]

diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index b034f13fda63f5892bbd9879d72f4b02e2632d69..29873d57a1e45fd989f6ff01dd4a2ae7320d93bb 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -54,6 +54,8 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xd09", "armv8-a+crc", "cortex-a73"},
     {"0xc14", "armv7-r", "cortex-r4"},
     {"0xc15", "armv7-r", "cortex-r5"},
+    {"0xc17", "armv7-r", "cortex-r7"},
+    {"0xc18", "armv7-r", "cortex-r8"},
     {"0xc20", "armv6-m", "cortex-m0"},
     {"0xc21", "armv6-m", "cortex-m1"},
     {"0xc23", "armv7-m", "cortex-m3"},

[PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 1613 bytes --]

Hi,

This patch adds support for ARMv8-R architecture [1] which was recently
announced. User level instructions for ARMv8-R are the same as those in
ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same
features as ARMv8-A in ARM backend.

[1] 
https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile

ChangeLog entries are as follow:

*** gcc/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-cpus.in (armv8-r, armv8-r+rcr): Add new entry.
	* config/arm/arm-cpu-cdata.h: Regenerate.
	* config/arm/arm-cpu-data.h: Regenerate.
	* config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
	enumerator.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARMv8-R and
	ARMv8-R with CRC extensions.
	* doc/invoke.texi: Mention -march=armv8-r and -march=armv8-r+crc
	options.  Document meaning of -march=armv8-r+rcr.

*** gcc/testsuite/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* lib/target-supports.exp: Generate
	check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
	and check_effective_target_arm_arch_v8r_multilib.

*** libgcc/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.

Tested by building an arm-none-eabi GCC cross-compiler targetting
ARMv8-R.

Is this ok for stage1?

Best regards,

Thomas

[-- Attachment #2: 2_add_armv8r_support.patch --]
[-- Type: text/x-patch, Size: 6987 bytes --]

diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h
index b3888120daa8494eb41bde0368122ad2f06d81af..0a122f5febaaceeeb5a405cb5a64e1edd9b044f3 100644
--- a/gcc/config/arm/arm-cpu-cdata.h
+++ b/gcc/config/arm/arm-cpu-cdata.h
@@ -1041,6 +1041,20 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
     },
   },
   {
+    "armv8-r",
+    {
+      ISA_ARMv8r,
+      isa_nobit
+    },
+  },
+  {
+    "armv8-r+crc",
+    {
+      ISA_ARMv8r,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
     "iwmmxt",
     {
       ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
index d6200f9bdc09a9d0c973853b0152a2800eaf2fe5..48c1d88032c1c5dc7c6cba71511f79fe9f2533ea 100644
--- a/gcc/config/arm/arm-cpu-data.h
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -1478,6 +1478,26 @@ static const struct processors all_architectures[] =
     NULL
   },
   {
+    "armv8-r", TARGET_CPU_cortexr4,
+    (TF_CO_PROC),
+    "8R", BASE_ARCH_8R,
+    {
+      ISA_ARMv8r,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8-r+crc", TARGET_CPU_cortexr4,
+    (TF_CO_PROC),
+    "8R", BASE_ARCH_8R,
+    {
+      ISA_ARMv8r,isa_bit_crc32,
+      isa_nobit
+    },
+    NULL
+  },
+  {
     "iwmmxt", TARGET_CPU_iwmmxt,
     (TF_LDSCHED | TF_STRONG | TF_XSCALE),
     "5TE", BASE_ARCH_5TE,
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index fc5d935182ba70de5ab2aefeec492318f42e95c5..be1f0ca4e38ae76683b77d8c3b79a066e62325d7 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -287,6 +287,20 @@ begin arch armv8-m.main+dsp
  isa ARMv8m_main bit_ARMv7em
 end arch armv8-m.main+dsp
 
+begin arch armv8-r
+ tune for cortex-r4
+ tune flags CO_PROC
+ base 8R
+ isa ARMv8r
+end arch armv8-r
+
+begin arch armv8-r+crc
+ tune for cortex-r4
+ tune flags CO_PROC
+ base 8R
+ isa ARMv8r bit_crc32
+end arch armv8-r+crc
+
 begin arch iwmmxt
  tune for iwmmxt
  tune flags LDSCHED STRONG XSCALE
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index 6050bca95587f68a3671dd2144cf845b83da3692..24ec398b346f8effb346235d6f3ab20eb6f70e0f 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -125,6 +125,7 @@ enum isa_feature
 #define ISA_ARMv8_2a	ISA_ARMv8_1a, isa_bit_ARMv8_2
 #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
 #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
+#define ISA_ARMv8r	ISA_ARMv8a
 
 /* List of all FPU bits to strip out if -mfpu is used to override the
    default.  isa_bit_fp16 is deliberately missing from this list.  */
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index cbcd85d9906d1fc797ab33b3d61969f32b9cc566..7bab5de5a39e9192c97851929b83175648158cdf 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -461,10 +461,16 @@ EnumValue
 Enum(arm_arch) String(armv8-m.main+dsp) Value(33)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt) Value(34)
+Enum(arm_arch) String(armv8-r) Value(34)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(35)
+Enum(arm_arch) String(armv8-r+crc) Value(35)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt) Value(36)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(37)
 
 Enum
 Name(arm_fpu) Type(enum fpu_type)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index e95eda358a54ca0804cfbb9acc0801835c3d7bfb..0b231214cd49b4217a3b9af05acb25b6e73a287b 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -373,7 +373,8 @@ enum base_architecture
   BASE_ARCH_7EM = 7,
   BASE_ARCH_8A = 8,
   BASE_ARCH_8M_BASE = 8,
-  BASE_ARCH_8M_MAIN = 8
+  BASE_ARCH_8M_MAIN = 8,
+  BASE_ARCH_8R = 8
 };
 
 /* The major revision number of the ARM Architecture implemented by the target.  */
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 56a4a4750428fa76cd5305b71a01d7ff7aa4256f..c394ac805c7577113ed72b31a06ff93dc7f5f490 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -99,6 +99,8 @@
    |march=armv8-m.base|mcpu=cortex-m23			\
    |march=armv8-m.main					\
    |march=armv8-m.main+dsp|mcpu=cortex-m33		\
+   |march-armv8-r					\
+   |march-armv8-r+crc					\
    :%{!r:--be8}}}"
 #else
 #define BE8_LINK_SPEC \
@@ -139,6 +141,8 @@
    |march=armv8-m.base|mcpu=cortex-m23			\
    |march=armv8-m.main					\
    |march=armv8-m.main+dsp|mcpu=cortex-m33		\
+   |march=armv8-r					\
+   |march=armv8-r+crc					\
    :%{!r:--be8}}}"
 #endif
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c205023d59cf9bb495c58a3a08461736cce1ad66..9ea580626749dc9d27bb72d56bbbef6a474a5055 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15147,7 +15147,8 @@ of the @option{-mcpu=} option.  Permissible names are: @samp{armv2},
 @samp{armv7}, @samp{armv7-a}, @samp{armv7-m}, @samp{armv7-r}, @samp{armv7e-m},
 @samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a},
 @samp{armv8.1-a+crc}, @samp{armv8-m.base}, @samp{armv8-m.main},
-@samp{armv8-m.main+dsp}, @samp{iwmmxt}, @samp{iwmmxt2}.
+@samp{armv8-m.main+dsp}, @samp{armv8-r}, , @samp{armv8-r+crc},
+@samp{iwmmxt}, @samp{iwmmxt2}.
 
 Architecture revisions older than @samp{armv4t} are deprecated.
 
@@ -15161,6 +15162,8 @@ compatibility.
 extensions.
 
 @option{-march=armv8-a+crc} enables code generation for the ARMv8-A
+architecture together with the optional CRC32 extensions.  Similarly,
+@option{-march=armv8-r+crc} enables code generation for the ARMv8-R
 architecture together with the optional CRC32 extensions.
 
 @option{-march=armv8.1-a} enables compiler support for the ARMv8.1-A
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 95a1c500c28a0612835436787a55c51bb1866fea..92cafc52b201d610fe30f57e020b29a736c01a09 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3781,7 +3781,8 @@ foreach { armfunc armflag armdef } {
 	v8_1a "-march=armv8.1a" __ARM_ARCH_8A__
 	v8_2a "-march=armv8.2a" __ARM_ARCH_8A__
 	v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft" __ARM_ARCH_8M_BASE__
-	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
+	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__
+	v8r "-march=armv8-r" __ARM_ARCH_8R__ } {
     eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] {
 	proc check_effective_target_arm_arch_FUNC_ok { } {
 	    if { [ string match "*-marm*" "FLAG" ] &&
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index 89ebebcd68a790c6bec140e4a8bd5a3b44dce291..8d8c3cead5f77f6dfeb2887e68483119ee3a400a 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -109,7 +109,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #endif
 
 #if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
-	|| defined(__ARM_ARCH_8M_MAIN__)
+	|| defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__)
 # define __ARM_ARCH__ 8
 #endif
 

[PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 806 bytes --]

Hi,

This patch adds support for the ARM Cortex-R52 processor rencently
announced.

[1] https://developer.arm.com/products/processors/cortex-r/cortex-r52

ChangeLog entry is as follows:

*** gcc/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-cpus.in (cortex-r52): Add new entry.
	* config/arm/arm-cpu.h: Regenerate.
	* config/arm/arm-cpu-cdata.h: Regenerate.
	* config/arm/arm-cpu-data.h: Regenerate.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARM Cortex-R52.
	* config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
	Cortex-R52.
	* doc/invoke.texi: Mention -mtune=cortex-r52.

Tested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52.

Is this ok for stage1?

Best regards,

Thomas

[-- Attachment #2: 3_add_cortexr52_support.patch --]
[-- Type: text/x-patch, Size: 4445 bytes --]

diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h
index 0a122f5febaaceeeb5a405cb5a64e1edd9b044f3..043b5b2db09146b5686a5fe602f907164f9d84c5 100644
--- a/gcc/config/arm/arm-cpu-cdata.h
+++ b/gcc/config/arm/arm-cpu-cdata.h
@@ -803,6 +803,13 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
     },
   },
   {
+    "cortex-r52",
+    {
+      ISA_ARMv8r,isa_bit_crc32,
+      isa_nobit
+    },
+  },
+  {
     "armv2",
     {
       ISA_ARMv2,isa_bit_mode26,
diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
index 48c1d88032c1c5dc7c6cba71511f79fe9f2533ea..0677132382fad2f1baf1fbdf5c0b03fe32f752e2 100644
--- a/gcc/config/arm/arm-cpu-data.h
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -1132,6 +1132,16 @@ static const struct processors all_cores[] =
     },
     &arm_v7m_tune
   },
+  {
+    "cortex-r52", TARGET_CPU_cortexr52,
+    (TF_LDSCHED),
+    "8R", BASE_ARCH_8R,
+    {
+      ISA_ARMv8r,isa_bit_crc32,
+      isa_nobit
+    },
+    &arm_cortex_tune
+  },
   {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
 };
 
diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h
index cd282db02f56f4416ff82eb3d8d569cd99fb0d41..4d6ea61d07dc98540f0f75679d8ef6f7eafc10bb 100644
--- a/gcc/config/arm/arm-cpu.h
+++ b/gcc/config/arm/arm-cpu.h
@@ -132,6 +132,7 @@ enum processor_type
   TARGET_CPU_cortexa73cortexa53,
   TARGET_CPU_cortexm23,
   TARGET_CPU_cortexm33,
+  TARGET_CPU_cortexr52,
   TARGET_CPU_arm_none
 };
 
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index be1f0ca4e38ae76683b77d8c3b79a066e62325d7..139aa561d3f918655978e44b5bcb6c0b50747a08 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1104,6 +1104,16 @@ begin cpu cortex-m33
  costs v7m
 end cpu cortex-m33
 
+
+# V8 R-profile implementations.
+begin cpu cortex-r52
+ cname cortexr52
+ tune flags LDSCHED
+ architecture armv8-r+crc
+ costs cortex
+end cpu cortex-r52
+
+
 # FPU entries
 # format:
 # begin fpu <name>
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 7bab5de5a39e9192c97851929b83175648158cdf..ccd1a7661fb97938ddea7670eebe1a0f48efb929 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -354,6 +354,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
 EnumValue
 Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
 
+EnumValue
+Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
+
 Enum
 Name(arm_arch) Type(int)
 Known ARM architectures (for use with the -march= option):
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index c394ac805c7577113ed72b31a06ff93dc7f5f490..c3dca1cd4833afd67e56a276ef0e9c1e17f4fae4 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -100,7 +100,7 @@
    |march=armv8-m.main					\
    |march=armv8-m.main+dsp|mcpu=cortex-m33		\
    |march-armv8-r					\
-   |march-armv8-r+crc					\
+   |march-armv8-r+crc|mcpu=cortex-r52			\
    :%{!r:--be8}}}"
 #else
 #define BE8_LINK_SPEC \
@@ -142,7 +142,7 @@
    |march=armv8-m.main					\
    |march=armv8-m.main+dsp|mcpu=cortex-m33		\
    |march=armv8-r					\
-   |march=armv8-r+crc					\
+   |march=armv8-r+crc|mcpu=cortex-r52			\
    :%{!r:--be8}}}"
 #endif
 
diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index 29873d57a1e45fd989f6ff01dd4a2ae7320d93bb..00f8128e6911a79f83da03bf731c1cc9127c7285 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -56,6 +56,7 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xc15", "armv7-r", "cortex-r5"},
     {"0xc17", "armv7-r", "cortex-r7"},
     {"0xc18", "armv7-r", "cortex-r8"},
+    {"0xd13", "armv8-r+crc", "cortex-r52"},
     {"0xc20", "armv6-m", "cortex-m0"},
     {"0xc21", "armv6-m", "cortex-m1"},
     {"0xc23", "armv7-m", "cortex-m3"},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9ea580626749dc9d27bb72d56bbbef6a474a5055..a871837426485dd6a87c541386964bf85dfafde7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15212,6 +15212,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
 @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4},
 @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
+@samp{cortex-r52},
 @samp{cortex-m33},
 @samp{cortex-m23},
 @samp{cortex-m7},

Re: [PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

[Christophe Lyon]

On 29 June 2017 at 15:52, Thomas Preudhomme
<thomas.preudhomme@foss.arm.com> wrote:
> Hi,
>
> This patch series adds support for the ARMv8-R architecture[1] and ARM
> Cortex-R52[2] to GCC. The patch series consist of the following patches:

Hi Thomas,

I think you need to rebase your patch because Richard's recent series
changed the contents
of arm-cpu-data.h and arm-cpu-cdata.h.

Why do you link armv8-r architecture definition to cortex-r4?

>
> [ 1/3] Add missing MIDR information for ARM Cortex-R7 and Cortex-R8
> processor
> [ 2/3] Add support for ARMv8-R architecture
> [ 3/3] Add support for ARM Cortex-R52
>
> [1]
> https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile
> [2] https://developer.arm.com/products/processors/cortex-r/cortex-r52

Re: [PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

[Thomas Preudhomme]

On 29/06/17 15:34, Christophe Lyon wrote:
> On 29 June 2017 at 15:52, Thomas Preudhomme
> <thomas.preudhomme@foss.arm.com> wrote:
>> Hi,
>>
>> This patch series adds support for the ARMv8-R architecture[1] and ARM
>> Cortex-R52[2] to GCC. The patch series consist of the following patches:
> 
> Hi Thomas,
> 
> I think you need to rebase your patch because Richard's recent series
> changed the contents
> of arm-cpu-data.h and arm-cpu-cdata.h.

Err yes indeed. Thanks!

> 
> Why do you link armv8-r architecture definition to cortex-r4?

I understand, where did I do such a thing?

Best regards,

Thomas

Re: [PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

[Christophe Lyon]

On 29 June 2017 at 16:37, Thomas Preudhomme
<thomas.preudhomme@foss.arm.com> wrote:
> On 29/06/17 15:34, Christophe Lyon wrote:
>>
>> On 29 June 2017 at 15:52, Thomas Preudhomme
>> <thomas.preudhomme@foss.arm.com> wrote:
>>>
>>> Hi,
>>>
>>> This patch series adds support for the ARMv8-R architecture[1] and ARM
>>> Cortex-R52[2] to GCC. The patch series consist of the following patches:
>>
>>
>> Hi Thomas,
>>
>> I think you need to rebase your patch because Richard's recent series
>> changed the contents
>> of arm-cpu-data.h and arm-cpu-cdata.h.
>
>
> Err yes indeed. Thanks!
>
>>
>> Why do you link armv8-r architecture definition to cortex-r4?
>
>
> I understand, where did I do such a thing?
>

In patch #2 you have:
diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
index d6200f9bdc09a9d0c973853b0152a2800eaf2fe5..48c1d88032c1c5dc7c6cba71511f79fe9f2533ea
100644
--- a/gcc/config/arm/arm-cpu-data.h
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -1478,6 +1478,26 @@ static const struct processors all_architectures[] =
     NULL
   },
   {
+    "armv8-r", TARGET_CPU_cortexr4,
+    (TF_CO_PROC),
+    "8R", BASE_ARCH_8R,
+    {
+      ISA_ARMv8r,
+      isa_nobit
+    },
+    NULL
+  },
+  {
+    "armv8-r+crc", TARGET_CPU_cortexr4,
+    (TF_CO_PROC),
+    "8R", BASE_ARCH_8R,
+    {
+      ISA_ARMv8r,isa_bit_crc32,
+      isa_nobit
+    },
+    NULL
+  },
+  {
     "iwmmxt", TARGET_CPU_iwmmxt,
     (TF_LDSCHED | TF_STRONG | TF_XSCALE),
     "5TE", BASE_ARCH_5TE,

Both entries point to TARGET_CPU_cortexr4. I guess that's because r52
is only defined in patch #3, but then why not update this in patch #3
are replace r4 with r52?

Not sure I'm very clear :-)

Thanks,

Christophe

> Best regards,
>
> Thomas

Re: [PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture

[Thomas Preudhomme]

Please ignore this patch. I'll respin the patch on a more recent GCC.

Best regards,

Thomas

On 29/06/17 14:55, Thomas Preudhomme wrote:
> Hi,
> 
> This patch adds support for ARMv8-R architecture [1] which was recently
> announced. User level instructions for ARMv8-R are the same as those in
> ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same
> features as ARMv8-A in ARM backend.
> 
> [1] 
> https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile 
> 
> 
> ChangeLog entries are as follow:
> 
> *** gcc/ChangeLog ***
> 
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>      * config/arm/arm-cpus.in (armv8-r, armv8-r+rcr): Add new entry.
>      * config/arm/arm-cpu-cdata.h: Regenerate.
>      * config/arm/arm-cpu-data.h: Regenerate.
>      * config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
>      * config/arm/arm-tables.opt: Regenerate.
>      * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
>      enumerator.
>      * config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARMv8-R and
>      ARMv8-R with CRC extensions.
>      * doc/invoke.texi: Mention -march=armv8-r and -march=armv8-r+crc
>      options.  Document meaning of -march=armv8-r+rcr.
> 
> *** gcc/testsuite/ChangeLog ***
> 
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>      * lib/target-supports.exp: Generate
>      check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
>      and check_effective_target_arm_arch_v8r_multilib.
> 
> *** libgcc/ChangeLog ***
> 
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>      * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.
> 
> Tested by building an arm-none-eabi GCC cross-compiler targetting
> ARMv8-R.
> 
> Is this ok for stage1?
> 
> Best regards,
> 
> Thomas

Re: [PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor

[Thomas Preudhomme]

Please ignore this patch. I'll respin the patch on a more recent GCC.

Best regards,

Thomas

On 29/06/17 14:56, Thomas Preudhomme wrote:
> Hi,
> 
> This patch adds support for the ARM Cortex-R52 processor rencently
> announced.
> 
> [1] https://developer.arm.com/products/processors/cortex-r/cortex-r52
> 
> ChangeLog entry is as follows:
> 
> *** gcc/ChangeLog ***
> 
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>      * config/arm/arm-cpus.in (cortex-r52): Add new entry.
>      * config/arm/arm-cpu.h: Regenerate.
>      * config/arm/arm-cpu-cdata.h: Regenerate.
>      * config/arm/arm-cpu-data.h: Regenerate.
>      * config/arm/arm-tables.opt: Regenerate.
>      * config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARM Cortex-R52.
>      * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
>      Cortex-R52.
>      * doc/invoke.texi: Mention -mtune=cortex-r52.
> 
> Tested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52.
> 
> Is this ok for stage1?
> 
> Best regards,
> 
> Thomas

Re: [PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

[Thomas Preudhomme]

On 29/06/17 16:12, Christophe Lyon wrote:
> On 29 June 2017 at 16:37, Thomas Preudhomme
>>
>>>
>>> Why do you link armv8-r architecture definition to cortex-r4?
>>
>>
>> I understand, where did I do such a thing?
>>
> 
> In patch #2 you have:
> diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
> index d6200f9bdc09a9d0c973853b0152a2800eaf2fe5..48c1d88032c1c5dc7c6cba71511f79fe9f2533ea
> 100644
> --- a/gcc/config/arm/arm-cpu-data.h
> +++ b/gcc/config/arm/arm-cpu-data.h
> @@ -1478,6 +1478,26 @@ static const struct processors all_architectures[] =
>       NULL
>     },
>     {
> +    "armv8-r", TARGET_CPU_cortexr4,
> +    (TF_CO_PROC),
> +    "8R", BASE_ARCH_8R,
> +    {
> +      ISA_ARMv8r,
> +      isa_nobit
> +    },
> +    NULL
> +  },
> +  {
> +    "armv8-r+crc", TARGET_CPU_cortexr4,
> +    (TF_CO_PROC),
> +    "8R", BASE_ARCH_8R,
> +    {
> +      ISA_ARMv8r,isa_bit_crc32,
> +      isa_nobit
> +    },
> +    NULL
> +  },
> +  {
>       "iwmmxt", TARGET_CPU_iwmmxt,
>       (TF_LDSCHED | TF_STRONG | TF_XSCALE),
>       "5TE", BASE_ARCH_5TE,
> 
> Both entries point to TARGET_CPU_cortexr4. I guess that's because r52
> is only defined in patch #3, but then why not update this in patch #3
> are replace r4 with r52?
> 
> Not sure I'm very clear :-)

You are. I must have forgotten about that setting when working on patch #3. I'll 
update this. Thanks for your vigilance :-)

Best regards,

Thomas

Re: [PATCH 1/3, GCC/ARM, ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 572 bytes --]

Ping?

Best regards,

Thomas

On 29/06/17 14:55, Thomas Preudhomme wrote:
> Hi,
> 
> The driver is missing MIDR information for processors ARM Cortex-R7 and
> Cortex-R8 to support -march/-mcpu/-mtune=native on the command line.
> This patch adds the missing information.
> 
> ChangeLog entry is as follows:
> 
> *** gcc/ChangeLog ***
> 
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>      * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
>      Cortex-R7 and Cortex-R8 processors.
> 
> Is this ok for master?
> 
> Best regards,
> 
> Thomas

[-- Attachment #2: 1_add_cortex_r7_r8_midr.patch --]
[-- Type: text/x-patch, Size: 623 bytes --]

diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index b034f13fda63f5892bbd9879d72f4b02e2632d69..29873d57a1e45fd989f6ff01dd4a2ae7320d93bb 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -54,6 +54,8 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xd09", "armv8-a+crc", "cortex-a73"},
     {"0xc14", "armv7-r", "cortex-r4"},
     {"0xc15", "armv7-r", "cortex-r5"},
+    {"0xc17", "armv7-r", "cortex-r7"},
+    {"0xc18", "armv7-r", "cortex-r8"},
     {"0xc20", "armv6-m", "cortex-m0"},
     {"0xc21", "armv6-m", "cortex-m1"},
     {"0xc23", "armv7-m", "cortex-m3"},

Re: [PATCH 1/3, GCC/ARM] Add MIDR info for ARM Cortex-R7 and Cortex-R8

[Kyrill Tkachov]

On 29/06/17 14:55, Thomas Preudhomme wrote:
> Hi,
>
> The driver is missing MIDR information for processors ARM Cortex-R7 and
> Cortex-R8 to support -march/-mcpu/-mtune=native on the command line.
> This patch adds the missing information.
>
> ChangeLog entry is as follows:
>
> *** gcc/ChangeLog ***
>
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>
>     * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
>     Cortex-R7 and Cortex-R8 processors.
>
> Is this ok for master?
>

Ok.
Thanks,
Kyrill

> Best regards,
>
> Thomas

Re: [PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 3012 bytes --]

Please find an updated patch in attachment. ChangeLog entry are now as follows:

*** gcc/ChangeLog ***

2017-07-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-cpus.in (armv8-r): Add new entry.
	* config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
	enumerator.
	* doc/invoke.texi: Mention -march=armv8-r and its extensions.

*** gcc/testsuite/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* lib/target-supports.exp: Generate
	check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
	and check_effective_target_arm_arch_v8r_multilib.

*** libgcc/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.


Tested by building an arm-none-eabi GCC cross-compiler targetting
ARMv8-R.

Is this ok for stage1?

Best regards,

Thomas

Best regards,

Thomas

On 29/06/17 16:13, Thomas Preudhomme wrote:
> Please ignore this patch. I'll respin the patch on a more recent GCC.
> 
> Best regards,
> 
> Thomas
> 
> On 29/06/17 14:55, Thomas Preudhomme wrote:
>> Hi,
>>
>> This patch adds support for ARMv8-R architecture [1] which was recently
>> announced. User level instructions for ARMv8-R are the same as those in
>> ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same
>> features as ARMv8-A in ARM backend.
>>
>> [1] 
>> https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile 
>>
>>
>> ChangeLog entries are as follow:
>>
>> *** gcc/ChangeLog ***
>>
>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>
>>      * config/arm/arm-cpus.in (armv8-r, armv8-r+rcr): Add new entry.
>>      * config/arm/arm-cpu-cdata.h: Regenerate.
>>      * config/arm/arm-cpu-data.h: Regenerate.
>>      * config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
>>      * config/arm/arm-tables.opt: Regenerate.
>>      * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
>>      enumerator.
>>      * config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARMv8-R and
>>      ARMv8-R with CRC extensions.
>>      * doc/invoke.texi: Mention -march=armv8-r and -march=armv8-r+crc
>>      options.  Document meaning of -march=armv8-r+rcr.
>>
>> *** gcc/testsuite/ChangeLog ***
>>
>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>
>>      * lib/target-supports.exp: Generate
>>      check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
>>      and check_effective_target_arm_arch_v8r_multilib.
>>
>> *** libgcc/ChangeLog ***
>>
>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>
>>      * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.
>>
>> Tested by building an arm-none-eabi GCC cross-compiler targetting
>> ARMv8-R.
>>
>> Is this ok for stage1?
>>
>> Best regards,
>>
>> Thomas

[-- Attachment #2: 2_add_armv8r_support.patch --]
[-- Type: text/x-patch, Size: 4958 bytes --]

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 946d543ebb29416da9b4928161607cccacaa78a7..f35128acb7d68c6a0592355b9d3d56ee8f826aca 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -380,6 +380,22 @@ begin arch armv8-m.main
  option nodsp remove bit_ARMv7em
 end arch armv8-m.main
 
+begin arch armv8-r
+ tune for cortex-r4
+ tune flags CO_PROC
+ base 8R
+ profile R
+ isa ARMv8r
+ option crc add bit_crc32
+# fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision
+# note: no fp option for fp-armv8 (d16) + double precision at the moment
+ option fp.sp add FP_ARMv8
+ option simd add FP_ARMv8 NEON
+ option crypto add FP_ARMv8 CRYPTO
+ option nocrypto remove ALL_CRYPTO
+ option nofp remove ALL_FP
+end arch armv8-r
+
 begin arch iwmmxt
  tune for iwmmxt
  tune flags LDSCHED STRONG XSCALE
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index c0c2ccee330f2313951e980c5d399ae5d21005d6..0d66a0400c517668db023fc66ff43e26d43add51 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -127,6 +127,7 @@ enum isa_feature
 #define ISA_ARMv8_2a	ISA_ARMv8_1a, isa_bit_ARMv8_2
 #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
 #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
+#define ISA_ARMv8r	ISA_ARMv8a
 
 /* List of all cryptographic extensions to stripout if crypto is
    disabled.  Currently, that's trivial, but we define it anyway for
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 5e2df9dd0716293fb551b6582a8c9c2c46fdaa90..51678c2566e841894c5c0e9c613c8c0f832e9988 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -455,10 +455,13 @@ EnumValue
 Enum(arm_arch) String(armv8-m.main) Value(30)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt) Value(31)
+Enum(arm_arch) String(armv8-r) Value(31)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(32)
+Enum(arm_arch) String(iwmmxt) Value(32)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(33)
 
 Enum
 Name(arm_fpu) Type(enum fpu_type)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index c803d4461c08436ef5f8468f6018e3226ccf33f8..315622212a5ce10d0c771535fe31f63c3be16444 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -384,7 +384,8 @@ enum base_architecture
   BASE_ARCH_7EM = 7,
   BASE_ARCH_8A = 8,
   BASE_ARCH_8M_BASE = 8,
-  BASE_ARCH_8M_MAIN = 8
+  BASE_ARCH_8M_MAIN = 8,
+  BASE_ARCH_8R = 8
 };
 
 /* The major revision number of the ARM Architecture implemented by the target.  */
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3e5cee8649ef9452e2a7e5a8603318ce11e2baff..d0b90503cedaae32bc83c7fd1fdd78b2a4d7184b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15218,6 +15218,7 @@ Permissible names are:
 @samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, 
 @samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a},
 @samp{armv7-r},
+@samp{armv8-r},
 @samp{armv6-m}, @samp{armv6s-m},
 @samp{armv7-m}, @samp{armv7e-m},
 @samp{armv8-m.base}, @samp{armv8-m.main},
@@ -15484,7 +15485,20 @@ The single- and double-precision floating-point instructions.
 
 @item +nofp
 Disable the floating-point extension.
+@end table
 
+@item armv8-r
+@table @samp
+@item +crc
+The Cyclic Redundancy Check (CRC) instructions.
+@item +simd
+The ARMv8 Advanced SIMD and floating-point instructions.
+@item +crypto
+The cryptographic instructions.
+@item +nocrypto
+Disable the cryptographic isntructions.
+@item +nofp
+Disable the floating-point, Advanced SIMD and cryptographic instructions.
 @end table
 
 @end table
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index fe5e77756404d603f04d674bb5ca872956d4b7ad..83d0c7ca441570dbf4d52641d12073f17d06e025 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3890,7 +3890,8 @@ foreach { armfunc armflag armdefs } {
 	v8_2a "-march=armv8.2a" __ARM_ARCH_8A__
 	v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
 		__ARM_ARCH_8M_BASE__
-	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
+	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__
+	v8r "-march=armv8-r" __ARM_ARCH_8R__ } {
     eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
 	proc check_effective_target_arm_arch_FUNC_ok { } {
 	    if { [ string match "*-marm*" "FLAG" ] &&
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index 89ebebcd68a790c6bec140e4a8bd5a3b44dce291..8d8c3cead5f77f6dfeb2887e68483119ee3a400a 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -109,7 +109,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #endif
 
 #if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
-	|| defined(__ARM_ARCH_8M_MAIN__)
+	|| defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__)
 # define __ARM_ARCH__ 8
 #endif
 

Re: [PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture

[Richard Earnshaw (lists)]

On 06/07/17 13:40, Thomas Preudhomme wrote:
> Please find an updated patch in attachment. ChangeLog entry are now as
> follows:
> 
> *** gcc/ChangeLog ***
> 
> 2017-07-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>     * config/arm/arm-cpus.in (armv8-r): Add new entry.
>     * config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
>     * config/arm/arm-tables.opt: Regenerate.
>     * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
>     enumerator.
>     * doc/invoke.texi: Mention -march=armv8-r and its extensions.
> 
> *** gcc/testsuite/ChangeLog ***
> 
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>     * lib/target-supports.exp: Generate
>     check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
>     and check_effective_target_arm_arch_v8r_multilib.
> 
> *** libgcc/ChangeLog ***
> 
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>     * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.
> 

OK.


R.

> 
> Tested by building an arm-none-eabi GCC cross-compiler targetting
> ARMv8-R.
> 
> Is this ok for stage1?
> 
> Best regards,
> 
> Thomas
> 
> Best regards,
> 
> Thomas
> 
> On 29/06/17 16:13, Thomas Preudhomme wrote:
>> Please ignore this patch. I'll respin the patch on a more recent GCC.
>>
>> Best regards,
>>
>> Thomas
>>
>> On 29/06/17 14:55, Thomas Preudhomme wrote:
>>> Hi,
>>>
>>> This patch adds support for ARMv8-R architecture [1] which was recently
>>> announced. User level instructions for ARMv8-R are the same as those in
>>> ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same
>>> features as ARMv8-A in ARM backend.
>>>
>>> [1]
>>> https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile
>>>
>>>
>>> ChangeLog entries are as follow:
>>>
>>> *** gcc/ChangeLog ***
>>>
>>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>>
>>>      * config/arm/arm-cpus.in (armv8-r, armv8-r+rcr): Add new entry.
>>>      * config/arm/arm-cpu-cdata.h: Regenerate.
>>>      * config/arm/arm-cpu-data.h: Regenerate.
>>>      * config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
>>>      * config/arm/arm-tables.opt: Regenerate.
>>>      * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
>>>      enumerator.
>>>      * config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARMv8-R and
>>>      ARMv8-R with CRC extensions.
>>>      * doc/invoke.texi: Mention -march=armv8-r and -march=armv8-r+crc
>>>      options.  Document meaning of -march=armv8-r+rcr.
>>>
>>> *** gcc/testsuite/ChangeLog ***
>>>
>>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>>
>>>      * lib/target-supports.exp: Generate
>>>      check_effective_target_arm_arch_v8r_ok,
>>> add_options_for_arm_arch_v8r
>>>      and check_effective_target_arm_arch_v8r_multilib.
>>>
>>> *** libgcc/ChangeLog ***
>>>
>>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>>
>>>      * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.
>>>
>>> Tested by building an arm-none-eabi GCC cross-compiler targetting
>>> ARMv8-R.
>>>
>>> Is this ok for stage1?
>>>
>>> Best regards,
>>>
>>> Thomas
> 
> 2_add_armv8r_support.patch
> 
> 
> diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
> index 946d543ebb29416da9b4928161607cccacaa78a7..f35128acb7d68c6a0592355b9d3d56ee8f826aca 100644
> --- a/gcc/config/arm/arm-cpus.in
> +++ b/gcc/config/arm/arm-cpus.in
> @@ -380,6 +380,22 @@ begin arch armv8-m.main
>   option nodsp remove bit_ARMv7em
>  end arch armv8-m.main
>  
> +begin arch armv8-r
> + tune for cortex-r4
> + tune flags CO_PROC
> + base 8R
> + profile R
> + isa ARMv8r
> + option crc add bit_crc32
> +# fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision
> +# note: no fp option for fp-armv8 (d16) + double precision at the moment
> + option fp.sp add FP_ARMv8
> + option simd add FP_ARMv8 NEON
> + option crypto add FP_ARMv8 CRYPTO
> + option nocrypto remove ALL_CRYPTO
> + option nofp remove ALL_FP
> +end arch armv8-r
> +
>  begin arch iwmmxt
>   tune for iwmmxt
>   tune flags LDSCHED STRONG XSCALE
> diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
> index c0c2ccee330f2313951e980c5d399ae5d21005d6..0d66a0400c517668db023fc66ff43e26d43add51 100644
> --- a/gcc/config/arm/arm-isa.h
> +++ b/gcc/config/arm/arm-isa.h
> @@ -127,6 +127,7 @@ enum isa_feature
>  #define ISA_ARMv8_2a	ISA_ARMv8_1a, isa_bit_ARMv8_2
>  #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
>  #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
> +#define ISA_ARMv8r	ISA_ARMv8a
>  
>  /* List of all cryptographic extensions to stripout if crypto is
>     disabled.  Currently, that's trivial, but we define it anyway for
> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
> index 5e2df9dd0716293fb551b6582a8c9c2c46fdaa90..51678c2566e841894c5c0e9c613c8c0f832e9988 100644
> --- a/gcc/config/arm/arm-tables.opt
> +++ b/gcc/config/arm/arm-tables.opt
> @@ -455,10 +455,13 @@ EnumValue
>  Enum(arm_arch) String(armv8-m.main) Value(30)
>  
>  EnumValue
> -Enum(arm_arch) String(iwmmxt) Value(31)
> +Enum(arm_arch) String(armv8-r) Value(31)
>  
>  EnumValue
> -Enum(arm_arch) String(iwmmxt2) Value(32)
> +Enum(arm_arch) String(iwmmxt) Value(32)
> +
> +EnumValue
> +Enum(arm_arch) String(iwmmxt2) Value(33)
>  
>  Enum
>  Name(arm_fpu) Type(enum fpu_type)
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index c803d4461c08436ef5f8468f6018e3226ccf33f8..315622212a5ce10d0c771535fe31f63c3be16444 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -384,7 +384,8 @@ enum base_architecture
>    BASE_ARCH_7EM = 7,
>    BASE_ARCH_8A = 8,
>    BASE_ARCH_8M_BASE = 8,
> -  BASE_ARCH_8M_MAIN = 8
> +  BASE_ARCH_8M_MAIN = 8,
> +  BASE_ARCH_8R = 8
>  };
>  
>  /* The major revision number of the ARM Architecture implemented by the target.  */
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 3e5cee8649ef9452e2a7e5a8603318ce11e2baff..d0b90503cedaae32bc83c7fd1fdd78b2a4d7184b 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -15218,6 +15218,7 @@ Permissible names are:
>  @samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, 
>  @samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a},
>  @samp{armv7-r},
> +@samp{armv8-r},
>  @samp{armv6-m}, @samp{armv6s-m},
>  @samp{armv7-m}, @samp{armv7e-m},
>  @samp{armv8-m.base}, @samp{armv8-m.main},
> @@ -15484,7 +15485,20 @@ The single- and double-precision floating-point instructions.
>  
>  @item +nofp
>  Disable the floating-point extension.
> +@end table
>  
> +@item armv8-r
> +@table @samp
> +@item +crc
> +The Cyclic Redundancy Check (CRC) instructions.
> +@item +simd
> +The ARMv8 Advanced SIMD and floating-point instructions.
> +@item +crypto
> +The cryptographic instructions.
> +@item +nocrypto
> +Disable the cryptographic isntructions.
> +@item +nofp
> +Disable the floating-point, Advanced SIMD and cryptographic instructions.
>  @end table
>  
>  @end table
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index fe5e77756404d603f04d674bb5ca872956d4b7ad..83d0c7ca441570dbf4d52641d12073f17d06e025 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -3890,7 +3890,8 @@ foreach { armfunc armflag armdefs } {
>  	v8_2a "-march=armv8.2a" __ARM_ARCH_8A__
>  	v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
>  		__ARM_ARCH_8M_BASE__
> -	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
> +	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__
> +	v8r "-march=armv8-r" __ARM_ARCH_8R__ } {
>      eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
>  	proc check_effective_target_arm_arch_FUNC_ok { } {
>  	    if { [ string match "*-marm*" "FLAG" ] &&
> diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
> index 89ebebcd68a790c6bec140e4a8bd5a3b44dce291..8d8c3cead5f77f6dfeb2887e68483119ee3a400a 100644
> --- a/libgcc/config/arm/lib1funcs.S
> +++ b/libgcc/config/arm/lib1funcs.S
> @@ -109,7 +109,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
>  #endif
>  
>  #if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
> -	|| defined(__ARM_ARCH_8M_MAIN__)
> +	|| defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__)
>  # define __ARM_ARCH__ 8
>  #endif
>  
> 

Re: [PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 1127 bytes --]

Hi,

On 29/06/17 16:13, Thomas Preudhomme wrote:
> Please ignore this patch. I'll respin the patch on a more recent GCC.

Please find an updated patch in attachment.

This patch adds support for the ARM Cortex-R52 processor rencently
announced.

[1] https://developer.arm.com/products/processors/cortex-r/cortex-r52

ChangeLog entry is as follows:

*** gcc/ChangeLog ***

2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-cpus.in (cortex-r52): Add new entry.
	(armv8-r): Set ARM Cortex-R52 as default CPU.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
	Cortex-R52.
	* doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp
	extension for -mcpu=cortex-r52.

Tested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52 and 
building an hello world with it. Also checked that the .fpu option created by 
GCC for -mcpu=cortex-r52 and -mcpu=cortex-r52+nofp.dp is as expected 
(respectively .fpu neon-fp-armv8 and .fpu fpv5-sp-d16

Is this ok for trunk?

Best regards,

Thomas

[-- Attachment #2: 3_add_cortexr52_support.patch --]
[-- Type: text/x-patch, Size: 3432 bytes --]

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index e2ff297aed7514073dbb3bf5ee86964f202e5a14..d009a9e18acb093aefe0f9d8d6de49489fc2325c 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -381,7 +381,7 @@ begin arch armv8-m.main
 end arch armv8-m.main
 
 begin arch armv8-r
- tune for cortex-r4
+ tune for cortex-r52
  tune flags CO_PROC
  base 8R
  profile R
@@ -1315,6 +1315,16 @@ begin cpu cortex-m33
  costs v7m
 end cpu cortex-m33
 
+# V8 R-profile implementations.
+begin cpu cortex-r52
+ cname cortexr52
+ tune flags LDSCHED
+ architecture armv8-r+crc+simd
+ fpu neon-fp-armv8
+ option nofp.dp remove FP_DBL ALL_SIMD
+ costs cortex
+end cpu cortex-r52
+
 # FPU entries
 # format:
 # begin fpu <name>
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 51678c2566e841894c5c0e9c613c8c0f832e9988..4e508b1555a77628ff6e7cfea39c98b87caa840a 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -357,6 +357,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
 EnumValue
 Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
 
+EnumValue
+Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
+
 Enum
 Name(arm_arch) Type(int)
 Known ARM architectures (for use with the -march= option):
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index ba2c7d8ecfdbf6966ebf04b680d587a0e057b161..1b3f7a94cc78fac8abf1042ef60c81a74eaf24eb 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -57,5 +57,6 @@
 	cortexa73,exynosm1,xgene1,
 	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
 	cortexa73cortexa53,cortexa55,cortexa75,
-	cortexa75cortexa55,cortexm23,cortexm33"
+	cortexa75cortexa55,cortexm23,cortexm33,
+	cortexr52"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index 16171d4e801af46ad549314d1f376e90d5bff57c..5c29b94caaba4ff6f89a191f1d8edcf10431c0b3 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -58,6 +58,7 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xc15", "armv7-r", "cortex-r5"},
     {"0xc17", "armv7-r", "cortex-r7"},
     {"0xc18", "armv7-r", "cortex-r8"},
+    {"0xd13", "armv8-r+crc", "cortex-r52"},
     {"0xc20", "armv6-m", "cortex-m0"},
     {"0xc21", "armv6-m", "cortex-m1"},
     {"0xc23", "armv7-m", "cortex-m3"},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e60edcae53ef3c995054b9b0229b5f0fccbb8462..a093b9bcf77b1f4b40992516e853826bb7d528d4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15538,7 +15538,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
 @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7},
-@samp{cortex-r8},
+@samp{cortex-r8}, @samp{cortex-r52},
 @samp{cortex-m33},
 @samp{cortex-m23},
 @samp{cortex-m7},
@@ -15628,7 +15628,7 @@ Disables the floating-point and SIMD instructions on
 
 @item +nofp.dp
 Disables the double-precision component of the floating-point instructions
-on @samp{cortex-r5} and @samp{cortex-m7}.
+on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}.
 
 @item +nosimd
 Disables the SIMD (but not floating-point) instructions on

Re: [PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor

[Kyrill Tkachov]

On 14/07/17 09:33, Thomas Preudhomme wrote:
> Hi,
>
> On 29/06/17 16:13, Thomas Preudhomme wrote:
>> Please ignore this patch. I'll respin the patch on a more recent GCC.
>
> Please find an updated patch in attachment.
>
> This patch adds support for the ARM Cortex-R52 processor rencently
> announced.
>
> [1] https://developer.arm.com/products/processors/cortex-r/cortex-r52
>
> ChangeLog entry is as follows:
>
> *** gcc/ChangeLog ***
>
> 2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>
>     * config/arm/arm-cpus.in (cortex-r52): Add new entry.
>     (armv8-r): Set ARM Cortex-R52 as default CPU.
>     * config/arm/arm-tables.opt: Regenerate.
>     * config/arm/arm-tune.md: Regenerate.
>     * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
>     Cortex-R52.
>     * doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp
>     extension for -mcpu=cortex-r52.
>
> Tested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52 and building an hello world with it. Also checked that the .fpu option created by GCC for -mcpu=cortex-r52 and -mcpu=cortex-r52+nofp.dp is as expected 
> (respectively .fpu neon-fp-armv8 and .fpu fpv5-sp-d16
>
> Is this ok for trunk?
>

Ok.
Thanks,
Kyrill

> Best regards,
>
> Thomas

[arm-embedded] [PATCH 1/3, GCC/ARM, ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 474 bytes --]

Hi,

We have decided to apply the following patch to the embedded-7-branch as a 
dependency patch to enable ARMv8-R support.

ChangeLog entry is as follows:

*** gcc/ChangeLog.arm ***

2017-09-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

      Backport from mainline
      2017-07-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

      * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
      Cortex-R7 and Cortex-R8 processors.

Best regards,

Thomas

[-- Attachment #2: Re: [PATCH 1/3, GCC/ARM, ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8.eml --]
[-- Type: message/rfc822, Size: 5387 bytes --]

[-- Attachment #2.1.1: Type: text/plain, Size: 572 bytes --]

Ping?

Best regards,

Thomas

On 29/06/17 14:55, Thomas Preudhomme wrote:
> Hi,
> 
> The driver is missing MIDR information for processors ARM Cortex-R7 and
> Cortex-R8 to support -march/-mcpu/-mtune=native on the command line.
> This patch adds the missing information.
> 
> ChangeLog entry is as follows:
> 
> *** gcc/ChangeLog ***
> 
> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> 
>      * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
>      Cortex-R7 and Cortex-R8 processors.
> 
> Is this ok for master?
> 
> Best regards,
> 
> Thomas

[-- Attachment #2.1.2: 1_add_cortex_r7_r8_midr.patch --]
[-- Type: text/x-patch, Size: 623 bytes --]

diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index b034f13fda63f5892bbd9879d72f4b02e2632d69..29873d57a1e45fd989f6ff01dd4a2ae7320d93bb 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -54,6 +54,8 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xd09", "armv8-a+crc", "cortex-a73"},
     {"0xc14", "armv7-r", "cortex-r4"},
     {"0xc15", "armv7-r", "cortex-r5"},
+    {"0xc17", "armv7-r", "cortex-r7"},
+    {"0xc18", "armv7-r", "cortex-r8"},
     {"0xc20", "armv6-m", "cortex-m0"},
     {"0xc21", "armv6-m", "cortex-m1"},
     {"0xc23", "armv7-m", "cortex-m3"},

[arm-embedded] [PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 1246 bytes --]

Hi,

We have decided to apply the following patch to the embedded-7-branch to enable 
ARMv8-R support.

ChangeLog entry is as follows:

*** gcc/ChangeLog.arm ***

2017-09-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

      Backport from mainline
      2017-07-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>

     * config/arm/arm-cpus.in (armv8-r): Add new entry.
     * config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
     * config/arm/arm-tables.opt: Regenerate.
     * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
     enumerator.
     * doc/invoke.texi: Mention -march=armv8-r and its extensions.

*** gcc/testsuite/ChangeLog ***


2017-09-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

      Backport from mainline
      2017-07-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>

     * lib/target-supports.exp: Generate
     check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
     and check_effective_target_arm_arch_v8r_multilib.

*** libgcc/ChangeLog ***


2017-09-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

      Backport from mainline
      2017-07-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>

     * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.

[-- Attachment #2: Re: [PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture.eml --]
[-- Type: message/rfc822, Size: 9325 bytes --]

[-- Attachment #2.1.1: Type: text/plain, Size: 3012 bytes --]

Please find an updated patch in attachment. ChangeLog entry are now as follows:

*** gcc/ChangeLog ***

2017-07-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-cpus.in (armv8-r): Add new entry.
	* config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
	enumerator.
	* doc/invoke.texi: Mention -march=armv8-r and its extensions.

*** gcc/testsuite/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* lib/target-supports.exp: Generate
	check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
	and check_effective_target_arm_arch_v8r_multilib.

*** libgcc/ChangeLog ***

2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.


Tested by building an arm-none-eabi GCC cross-compiler targetting
ARMv8-R.

Is this ok for stage1?

Best regards,

Thomas

Best regards,

Thomas

On 29/06/17 16:13, Thomas Preudhomme wrote:
> Please ignore this patch. I'll respin the patch on a more recent GCC.
> 
> Best regards,
> 
> Thomas
> 
> On 29/06/17 14:55, Thomas Preudhomme wrote:
>> Hi,
>>
>> This patch adds support for ARMv8-R architecture [1] which was recently
>> announced. User level instructions for ARMv8-R are the same as those in
>> ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same
>> features as ARMv8-A in ARM backend.
>>
>> [1] 
>> https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile 
>>
>>
>> ChangeLog entries are as follow:
>>
>> *** gcc/ChangeLog ***
>>
>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>
>>      * config/arm/arm-cpus.in (armv8-r, armv8-r+rcr): Add new entry.
>>      * config/arm/arm-cpu-cdata.h: Regenerate.
>>      * config/arm/arm-cpu-data.h: Regenerate.
>>      * config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
>>      * config/arm/arm-tables.opt: Regenerate.
>>      * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
>>      enumerator.
>>      * config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARMv8-R and
>>      ARMv8-R with CRC extensions.
>>      * doc/invoke.texi: Mention -march=armv8-r and -march=armv8-r+crc
>>      options.  Document meaning of -march=armv8-r+rcr.
>>
>> *** gcc/testsuite/ChangeLog ***
>>
>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>
>>      * lib/target-supports.exp: Generate
>>      check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
>>      and check_effective_target_arm_arch_v8r_multilib.
>>
>> *** libgcc/ChangeLog ***
>>
>> 2017-01-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>>
>>      * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.
>>
>> Tested by building an arm-none-eabi GCC cross-compiler targetting
>> ARMv8-R.
>>
>> Is this ok for stage1?
>>
>> Best regards,
>>
>> Thomas

[-- Attachment #2.1.2: 2_add_armv8r_support.patch --]
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diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 946d543ebb29416da9b4928161607cccacaa78a7..f35128acb7d68c6a0592355b9d3d56ee8f826aca 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -380,6 +380,22 @@ begin arch armv8-m.main
  option nodsp remove bit_ARMv7em
 end arch armv8-m.main
 
+begin arch armv8-r
+ tune for cortex-r4
+ tune flags CO_PROC
+ base 8R
+ profile R
+ isa ARMv8r
+ option crc add bit_crc32
+# fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision
+# note: no fp option for fp-armv8 (d16) + double precision at the moment
+ option fp.sp add FP_ARMv8
+ option simd add FP_ARMv8 NEON
+ option crypto add FP_ARMv8 CRYPTO
+ option nocrypto remove ALL_CRYPTO
+ option nofp remove ALL_FP
+end arch armv8-r
+
 begin arch iwmmxt
  tune for iwmmxt
  tune flags LDSCHED STRONG XSCALE
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index c0c2ccee330f2313951e980c5d399ae5d21005d6..0d66a0400c517668db023fc66ff43e26d43add51 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -127,6 +127,7 @@ enum isa_feature
 #define ISA_ARMv8_2a	ISA_ARMv8_1a, isa_bit_ARMv8_2
 #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
 #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
+#define ISA_ARMv8r	ISA_ARMv8a
 
 /* List of all cryptographic extensions to stripout if crypto is
    disabled.  Currently, that's trivial, but we define it anyway for
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 5e2df9dd0716293fb551b6582a8c9c2c46fdaa90..51678c2566e841894c5c0e9c613c8c0f832e9988 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -455,10 +455,13 @@ EnumValue
 Enum(arm_arch) String(armv8-m.main) Value(30)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt) Value(31)
+Enum(arm_arch) String(armv8-r) Value(31)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(32)
+Enum(arm_arch) String(iwmmxt) Value(32)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(33)
 
 Enum
 Name(arm_fpu) Type(enum fpu_type)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index c803d4461c08436ef5f8468f6018e3226ccf33f8..315622212a5ce10d0c771535fe31f63c3be16444 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -384,7 +384,8 @@ enum base_architecture
   BASE_ARCH_7EM = 7,
   BASE_ARCH_8A = 8,
   BASE_ARCH_8M_BASE = 8,
-  BASE_ARCH_8M_MAIN = 8
+  BASE_ARCH_8M_MAIN = 8,
+  BASE_ARCH_8R = 8
 };
 
 /* The major revision number of the ARM Architecture implemented by the target.  */
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3e5cee8649ef9452e2a7e5a8603318ce11e2baff..d0b90503cedaae32bc83c7fd1fdd78b2a4d7184b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15218,6 +15218,7 @@ Permissible names are:
 @samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, 
 @samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a},
 @samp{armv7-r},
+@samp{armv8-r},
 @samp{armv6-m}, @samp{armv6s-m},
 @samp{armv7-m}, @samp{armv7e-m},
 @samp{armv8-m.base}, @samp{armv8-m.main},
@@ -15484,7 +15485,20 @@ The single- and double-precision floating-point instructions.
 
 @item +nofp
 Disable the floating-point extension.
+@end table
 
+@item armv8-r
+@table @samp
+@item +crc
+The Cyclic Redundancy Check (CRC) instructions.
+@item +simd
+The ARMv8 Advanced SIMD and floating-point instructions.
+@item +crypto
+The cryptographic instructions.
+@item +nocrypto
+Disable the cryptographic isntructions.
+@item +nofp
+Disable the floating-point, Advanced SIMD and cryptographic instructions.
 @end table
 
 @end table
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index fe5e77756404d603f04d674bb5ca872956d4b7ad..83d0c7ca441570dbf4d52641d12073f17d06e025 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3890,7 +3890,8 @@ foreach { armfunc armflag armdefs } {
 	v8_2a "-march=armv8.2a" __ARM_ARCH_8A__
 	v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
 		__ARM_ARCH_8M_BASE__
-	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
+	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__
+	v8r "-march=armv8-r" __ARM_ARCH_8R__ } {
     eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
 	proc check_effective_target_arm_arch_FUNC_ok { } {
 	    if { [ string match "*-marm*" "FLAG" ] &&
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index 89ebebcd68a790c6bec140e4a8bd5a3b44dce291..8d8c3cead5f77f6dfeb2887e68483119ee3a400a 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -109,7 +109,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #endif
 
 #if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
-	|| defined(__ARM_ARCH_8M_MAIN__)
+	|| defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__)
 # define __ARM_ARCH__ 8
 #endif
 

[arm-embedded] [PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor

[Thomas Preudhomme]

[-- Attachment #1: Type: text/plain, Size: 713 bytes --]

Hi,

We have decided to apply the following patch to the embedded-7-branch to enable 
Arm Cortex-R52 support.

*** gcc/ChangeLog.arm ***

2017-09-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

      Backport from mainline
      2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

     * config/arm/arm-cpus.in (cortex-r52): Add new entry.
     (armv8-r): Set ARM Cortex-R52 as default CPU.
     * config/arm/arm-tables.opt: Regenerate.
     * config/arm/arm-tune.md: Regenerate.
     * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
     Cortex-R52.
     * doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp
     extension for -mcpu=cortex-r52.

Best regards,

Thomas

[-- Attachment #2: Re: [PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor.eml --]
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[-- Attachment #2.1.1: Type: text/plain, Size: 1127 bytes --]

Hi,

On 29/06/17 16:13, Thomas Preudhomme wrote:
> Please ignore this patch. I'll respin the patch on a more recent GCC.

Please find an updated patch in attachment.

This patch adds support for the ARM Cortex-R52 processor rencently
announced.

[1] https://developer.arm.com/products/processors/cortex-r/cortex-r52

ChangeLog entry is as follows:

*** gcc/ChangeLog ***

2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-cpus.in (cortex-r52): Add new entry.
	(armv8-r): Set ARM Cortex-R52 as default CPU.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
	Cortex-R52.
	* doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp
	extension for -mcpu=cortex-r52.

Tested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52 and 
building an hello world with it. Also checked that the .fpu option created by 
GCC for -mcpu=cortex-r52 and -mcpu=cortex-r52+nofp.dp is as expected 
(respectively .fpu neon-fp-armv8 and .fpu fpv5-sp-d16

Is this ok for trunk?

Best regards,

Thomas

[-- Attachment #2.1.2: 3_add_cortexr52_support.patch --]
[-- Type: text/x-patch, Size: 3432 bytes --]

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index e2ff297aed7514073dbb3bf5ee86964f202e5a14..d009a9e18acb093aefe0f9d8d6de49489fc2325c 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -381,7 +381,7 @@ begin arch armv8-m.main
 end arch armv8-m.main
 
 begin arch armv8-r
- tune for cortex-r4
+ tune for cortex-r52
  tune flags CO_PROC
  base 8R
  profile R
@@ -1315,6 +1315,16 @@ begin cpu cortex-m33
  costs v7m
 end cpu cortex-m33
 
+# V8 R-profile implementations.
+begin cpu cortex-r52
+ cname cortexr52
+ tune flags LDSCHED
+ architecture armv8-r+crc+simd
+ fpu neon-fp-armv8
+ option nofp.dp remove FP_DBL ALL_SIMD
+ costs cortex
+end cpu cortex-r52
+
 # FPU entries
 # format:
 # begin fpu <name>
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 51678c2566e841894c5c0e9c613c8c0f832e9988..4e508b1555a77628ff6e7cfea39c98b87caa840a 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -357,6 +357,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
 EnumValue
 Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
 
+EnumValue
+Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
+
 Enum
 Name(arm_arch) Type(int)
 Known ARM architectures (for use with the -march= option):
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index ba2c7d8ecfdbf6966ebf04b680d587a0e057b161..1b3f7a94cc78fac8abf1042ef60c81a74eaf24eb 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -57,5 +57,6 @@
 	cortexa73,exynosm1,xgene1,
 	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
 	cortexa73cortexa53,cortexa55,cortexa75,
-	cortexa75cortexa55,cortexm23,cortexm33"
+	cortexa75cortexa55,cortexm23,cortexm33,
+	cortexr52"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index 16171d4e801af46ad549314d1f376e90d5bff57c..5c29b94caaba4ff6f89a191f1d8edcf10431c0b3 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -58,6 +58,7 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xc15", "armv7-r", "cortex-r5"},
     {"0xc17", "armv7-r", "cortex-r7"},
     {"0xc18", "armv7-r", "cortex-r8"},
+    {"0xd13", "armv8-r+crc", "cortex-r52"},
     {"0xc20", "armv6-m", "cortex-m0"},
     {"0xc21", "armv6-m", "cortex-m1"},
     {"0xc23", "armv7-m", "cortex-m3"},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e60edcae53ef3c995054b9b0229b5f0fccbb8462..a093b9bcf77b1f4b40992516e853826bb7d528d4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15538,7 +15538,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
 @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7},
-@samp{cortex-r8},
+@samp{cortex-r8}, @samp{cortex-r52},
 @samp{cortex-m33},
 @samp{cortex-m23},
 @samp{cortex-m7},
@@ -15628,7 +15628,7 @@ Disables the floating-point and SIMD instructions on
 
 @item +nofp.dp
 Disables the double-precision component of the floating-point instructions
-on @samp{cortex-r5} and @samp{cortex-m7}.
+on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}.
 
 @item +nosimd
 Disables the SIMD (but not floating-point) instructions on