From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by sourceware.org (Postfix) with ESMTPS id 652993894C11 for ; Tue, 15 Nov 2022 12:51:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 652993894C11 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=ispras.ru Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ispras.ru Received: from [10.10.3.121] (unknown [10.10.3.121]) by mail.ispras.ru (Postfix) with ESMTPS id ECDB5419E9CA; Tue, 15 Nov 2022 12:51:04 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru ECDB5419E9CA Date: Tue, 15 Nov 2022 15:51:04 +0300 (MSK) From: Alexander Monakov To: "Joshi, Tejas Sanjay" cc: "gcc-patches@gcc.gnu.org" , "honza.hubicka@gmail.com" , "Kumar, Venkataramanan" Subject: RE: [PATCH][X86_64] Separate znver4 insn reservations from older znvers In-Reply-To: Message-ID: <8e489785-b181-fbcf-e029-cd75796a6f28@ispras.ru> References: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 15 Nov 2022, Joshi, Tejas Sanjay wrote: > > > +;; AVX instructions > > > +(define_insn_reservation "znver4_sse_log" 1 > > > + (and (eq_attr "cpu" "znver4") > > > + (and (eq_attr "type" "sselog,sselog1") > > > + (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF") > > > + (eq_attr "memory" "none")))) > > > + "znver4-direct,znver4-fpu") > > > + > > > +(define_insn_reservation "znver4_sse_log_evex" 1 > > > + (and (eq_attr "cpu" "znver4") > > > + (and (eq_attr "type" "sselog,sselog1") > > > + (and (eq_attr "mode" "V16SF,V8DF") > > > + (eq_attr "memory" "none")))) > > > + > > > +"znver4-direct,znver4-fpu0+znver4-fpu1|znver4-fpu2+znver4-fpu3") > > > + > > > > This is an AVX512 instruction, and you're modeling that it occupies two ports > > at once and thus has half throughput, but later in the AVX512 section: > > > > > +;; AVX512 instructions > > > +(define_insn_reservation "znver4_sse_mul_evex" 3 > > > + (and (eq_attr "cpu" "znver4") > > > + (and (eq_attr "type" "ssemul") > > > + (and (eq_attr "mode" "V16SF,V8DF") > > > + (eq_attr "memory" "none")))) > > > + "znver4-double,znver4-fpu0|znver4-fpu3") > > > > none of the instructions are modeled this way. If that's on purpose, can you > > add a comment? It's surprising, since generally AVX512 has half throughput > > compared to AVX256 on Zen 4, but the model doesn't seem to reflect that. > > > > +"znver4-direct,znver4-fpu0+znver4-fpu1|znver4-fpu2+znver4-fpu3") > > AVX512 instructions (512-bitwide) occupy 2 consecutive cycles in the pipes > they execute. So, it should be modelled as shown below: > > (define_insn_reservation "znver4_sse_log_evex" 1 > (and (eq_attr "cpu" "znver4") > (and (eq_attr "type" "sselog") > (and (eq_attr "mode" "V16SF,V8DF,XI") > (eq_attr "memory" "none")))) > "znver4-double,(znver4-fpu)*2") I think instead of (znver4-fpu)*2 there should be znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2 assuming the instruction occupies the same pipe on both cycles (your variant models as if it can move from one pipe to another). > (define_insn_reservation "znver4_sse_mul_evex" 3 > (and (eq_attr "cpu" "znver4") > (and (eq_attr "type" "ssemul") > (and (eq_attr "mode" "V16SF,V8DF") > (eq_attr "memory" "none")))) > "znver4-double,(znver4-fpu0|znver4-fpu1)*2") Likewise here, znver4-fpu0*2|znver4-fpu1*2. > Doing this way increased the insn-automata.cc size from 201402 lines to 212189. Please reevaluate on top of my patches, the impact will be different. > Hope it is a tolerable increase or do you have any suggestions? Please take the corrections above into account. Also I think it's better to use znver4-direct rather than znver4-double for AVX512 instructions, because they are decoded as one uop, not two (it won't make a practical difference due to a "Fix me", but it's a simple improvement). Thanks. Alexander