From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
To: GCC Patches <gcc-patches@gcc.gnu.org>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH 2/2] xtensa: Merge '*addx' and '*subx' insn patterns into one
Date: Mon, 22 May 2023 16:04:37 +0900 [thread overview]
Message-ID: <8f4e2726-0844-3dd0-8a27-7fb669db8f76@yahoo.co.jp> (raw)
In-Reply-To: <8f4e2726-0844-3dd0-8a27-7fb669db8f76.ref@yahoo.co.jp>
By making use of the 'addsub_operator' added in the last patch.
gcc/ChangeLog:
* config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
and change to also accept '*subx' pattern.
(*subx): Remove.
---
gcc/config/xtensa/xtensa.md | 31 +++++++++++++------------------
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index bd4614e4be0..f3313266645 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -170,15 +170,24 @@
(set_attr "mode" "SI")
(set_attr "length" "2,2,3,3,3")])
-(define_insn "*addx"
+(define_insn "*addsubx"
[(set (match_operand:SI 0 "register_operand" "=a")
- (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operator:SI 4 "addsub_operator"
+ [(ashift:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 3 "addsubx_operand" "i"))
- (match_operand:SI 2 "register_operand" "r")))]
+ (match_operand:SI 2 "register_operand" "r")]))]
"TARGET_ADDX"
{
operands[3] = GEN_INT (1 << INTVAL (operands[3]));
- return "addx%3\t%0, %1, %2";
+ switch (GET_CODE (operands[4]))
+ {
+ case PLUS:
+ return "addx%3\t%0, %1, %2";
+ case MINUS:
+ return "subx%3\t%0, %1, %2";
+ default:
+ gcc_unreachable ();
+ }
}
[(set_attr "type" "arith")
(set_attr "mode" "SI")
@@ -207,20 +216,6 @@
(set_attr "mode" "SI")
(set_attr "length" "3")])
-(define_insn "*subx"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 3 "addsubx_operand" "i"))
- (match_operand:SI 2 "register_operand" "r")))]
- "TARGET_ADDX"
-{
- operands[3] = GEN_INT (1 << INTVAL (operands[3]));
- return "subx%3\t%0, %1, %2";
-}
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "3")])
-
(define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(minus:SF (match_operand:SF 1 "register_operand" "f")
--
2.30.2
next parent reply other threads:[~2023-05-22 7:06 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <8f4e2726-0844-3dd0-8a27-7fb669db8f76.ref@yahoo.co.jp>
2023-05-22 7:04 ` Takayuki 'January June' Suwa [this message]
2023-05-23 20:05 ` Max Filippov
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