Re: [PATCH v1] RISC-V: Bugfix for legitimize address PR/111634

[Jeff Law <jeffreyalaw@gmail.com>]

On 10/6/23 22:49, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> Given we have RTL as below.
> 
> (plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
>                    (const_int 8 [0x8]))
>           (lo_sum:DI (reg:DI 167)
>                      (symbol_ref:DI ("f") [flags 0x86] <var_decl 0x7fa96ea1cc60 f>)
> ))
> 
> When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case,
> the fp will be the lo_sum operand as above. We have assumption that the fp
> is reg but actually not here. It will have ICE when building with option
> --enable-checking=rtl.
> 
> This patch would like to fix it by adding the REG_P to ensure the operand
> is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered this
> fix when build with --enable-checking=rtl.
> 
> 	PR target/111634
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_legitimize_address): Bugfix.
OK, though the ChangeLog entry could be better.  Perhaps

	* config/riscv/riscv.cc (riscv_legitimize_address): Ensure
	object is a REG before extracting its register number.


Jeff