From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: Richard Biener <richard.guenther@gmail.com>
Cc: gcc-patches@gcc.gnu.org, Richard Sandiford <richard.sandiford@arm.com>
Subject: Re: [PATCH 6/8] vect: Add vector_mode paramater to simd_clone_usable
Date: Thu, 28 Sep 2023 16:57:34 +0100 [thread overview]
Message-ID: <9092d486-d658-c5df-f05c-04f781452395@arm.com> (raw)
In-Reply-To: <CAFiYyc2ia-Mcp8ek3rETN5Rt4rgPw-dZmHneCbyUuZxpGxEB7Q@mail.gmail.com>
On 31/08/2023 07:39, Richard Biener wrote:
> On Wed, Aug 30, 2023 at 5:02 PM Andre Vieira (lists)
> <andre.simoesdiasvieira@arm.com> wrote:
>>
>>
>>
>> On 30/08/2023 14:01, Richard Biener wrote:
>>> On Wed, Aug 30, 2023 at 11:15 AM Andre Vieira (lists) via Gcc-patches
>>> <gcc-patches@gcc.gnu.org> wrote:
>>>>
>>>> This patch adds a machine_mode parameter to the TARGET_SIMD_CLONE_USABLE
>>>> hook to enable rejecting SVE modes when the target architecture does not
>>>> support SVE.
>>>
>>> How does the graph node of the SIMD clone lack this information? That is, it
>>> should have information on the types (and thus modes) for all formal arguments
>>> and return values already, no? At least the target would know how to
>>> instantiate
>>> it if it's not readily available at the point of use.
>>>
>>
>> Yes it does, but that's the modes the simd clone itself uses, it does
>> not know what vector_mode we are currently vectorizing for. Which is
>> exactly why we need the vinfo's vector_mode to make sure the simd clone
>> and its types are compatible with the vector mode.
>>
>> In practice, to make sure that a SVE simd clones are only used in loops
>> being vectorized for SVE modes. Having said that... I just realized that
>> the simdlen check already takes care of that currently...
>>
>> by simdlen check I mean the one that writes off simdclones that match:
>> if (!constant_multiple_p (vf, n->simdclone->simdlen, &num_calls)
>>
>> However, when using -msve-vector-bits this will become an issue, as the
>> VF will be constant and we will match NEON simdclones. This requires
>> some further attention though given that we now also reject the use of
>> SVE simdclones when using -msve-vector-bits, and I'm not entirely sure
>> we should...
>
> Hmm, but vectorizable_simdclone should check for compatible types here
> and if they are compatible why should we reject them? Are -msve-vector-bits
> "SVE" modes different from "NEON" modes? I suppose not, because otherwise
> the type compatibility check would say incompatible.
>
Prior to transformation we do all checks on the original scalar values,
not the vector types. But I do believe you are right in that we don't
need to pass the vector_mode. The simdlen check should be enough and if
the length is the same or a multiple of the rest of the could should be
able to deal with that and any conversions when dealing with things like
SVE types that require the attribute.
I'll update the patch series soon and after that I'll look at how this
reacts to -msve-vector-bits in more detail.
Thanks,
Andre
next prev parent reply other threads:[~2023-09-28 15:57 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-30 8:49 aarch64, vect, omp: Add SVE support for simd clones [PR 96342] Andre Vieira (lists)
2023-08-30 9:06 ` [PATCH 1/8] parloops: Copy target and optimizations when creating a function clone Andre Vieira (lists)
2023-08-30 12:31 ` Richard Biener
2023-10-18 14:40 ` Andre Vieira (lists)
2023-08-30 9:08 ` [Patch 2/8] parloops: Allow poly nit and bound Andre Vieira (lists)
2023-08-30 12:32 ` Richard Biener
2023-10-18 14:40 ` Andre Vieira (lists)
2023-08-30 9:10 ` [Patch 3/8] vect: Fix vect_get_smallest_scalar_type for simd clones Andre Vieira (lists)
2023-08-30 12:54 ` Richard Biener
2023-10-18 14:40 ` Andre Vieira (lists)
2023-10-19 12:07 ` Richard Biener
2023-08-30 9:11 ` [PATCH 4/8] vect: don't allow fully masked loops with non-masked simd clones [PR 110485] Andre Vieira (lists)
2023-08-30 12:54 ` Richard Biener
2023-10-18 14:40 ` Andre Vieira (lists)
2023-10-19 12:06 ` Richard Biener
2023-08-30 9:13 ` [PATCH 5/8] vect: Use inbranch simdclones in masked loops Andre Vieira (lists)
2023-10-18 14:41 ` Andre Vieira (lists)
2023-10-19 12:17 ` Richard Biener
2023-08-30 9:14 ` [PATCH 6/8] vect: Add vector_mode paramater to simd_clone_usable Andre Vieira (lists)
2023-08-30 9:17 ` Andre Vieira (lists)
2023-08-30 13:01 ` Richard Biener
2023-08-30 15:02 ` Andre Vieira (lists)
2023-08-31 6:39 ` Richard Biener
2023-09-28 15:57 ` Andre Vieira (lists) [this message]
2023-08-30 9:17 ` [PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM Andre Vieira (lists)
2023-08-30 13:04 ` Richard Biener
2023-10-04 10:32 ` Andre Vieira (lists)
2023-10-04 10:41 ` Richard Biener
2023-10-04 12:40 ` Andre Vieira (lists)
2023-10-18 14:41 ` [PATCH6/8] omp: Reorder call for TARGET_SIMD_CLONE_ADJUST (was Re: [PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM) Andre Vieira (lists)
2023-10-30 18:34 ` Andre Vieira (lists)
2023-10-31 7:59 ` Richard Biener
2023-12-08 10:35 ` Jakub Jelinek
2023-08-30 9:19 ` [PATCH 8/8] aarch64: Add SVE support for simd clones [PR 96342] Andre Vieira (lists)
2023-10-18 14:41 ` Andre Vieira (lists)
2023-11-29 17:01 ` Richard Sandiford
2023-12-01 16:39 ` Andre Vieira (lists)
2023-10-18 14:40 ` aarch64, vect, omp: " Andre Vieira (lists)
2023-10-18 14:41 ` [PATCH 0/8] omp: Replace simd_clone_subparts with TYPE_VECTOR_SUBPARTS Andre Vieira (lists)
2023-10-19 7:10 ` Richard Biener
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