* [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV
@ 2023-12-21 2:25 pan2.li
2023-12-21 19:16 ` Jeff Law
2023-12-23 12:39 ` [PATCH v2] " pan2.li
0 siblings, 2 replies; 7+ messages in thread
From: pan2.li @ 2023-12-21 2:25 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng, jeffreyalaw,
richard.guenther, tamar.christina
From: Pan Li <pan2.li@intel.com>
This patch would like to XFail the signbit-5 run test case for
the RVV. Given the case has one limitation like "This test does not
work when the truth type does not match vector type." in the beginning
of the test file. Aka, the RVV vector truth type is not integer type.
The target board of riscv-sim like below will pick up `-march=rv64gcv`
when building the run test elf. Thus, the RVV cannot bypass this test
case like aarch64_sve with additional option `-march=armv8-a`.
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`.
The signbit-5.c passed test with below configurations.
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-5.c: XFail for the riscv.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.dg/signbit-5.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/signbit-5.c b/gcc/testsuite/gcc.dg/signbit-5.c
index 0fad56c0ea8..e358d23a192 100644
--- a/gcc/testsuite/gcc.dg/signbit-5.c
+++ b/gcc/testsuite/gcc.dg/signbit-5.c
@@ -5,6 +5,7 @@
/* { dg-additional-options "-mno-avx512f" { target { i?86-*-* x86_64-*-* } } } */
/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
/* { dg-xfail-run-if "truth type does not match vector type" { amdgcn-*-* } } */
+/* { dg-xfail-run-if "truth type does not match vector type" { riscv*-*-* } } */
#include <stdint.h>
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV
2023-12-21 2:25 [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV pan2.li
@ 2023-12-21 19:16 ` Jeff Law
2023-12-21 22:44 ` 钟居哲
2023-12-23 12:39 ` [PATCH v2] " pan2.li
1 sibling, 1 reply; 7+ messages in thread
From: Jeff Law @ 2023-12-21 19:16 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: juzhe.zhong, yanzhang.wang, kito.cheng, richard.guenther,
tamar.christina
On 12/20/23 19:25, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to XFail the signbit-5 run test case for
> the RVV. Given the case has one limitation like "This test does not
> work when the truth type does not match vector type." in the beginning
> of the test file. Aka, the RVV vector truth type is not integer type.
>
> The target board of riscv-sim like below will pick up `-march=rv64gcv`
> when building the run test elf. Thus, the RVV cannot bypass this test
> case like aarch64_sve with additional option `-march=armv8-a`.
>
> riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
>
> For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`.
But isn't that just going to turn this into an XPASS when vector is not
enabled?
Looking at a recent rv64gc run of mine:
> PASS: gcc.dg/signbit-5.c (test for excess errors)
> PASS: gcc.dg/signbit-5.c execution test
Ideally we'd find a way to handle with and without vector.
jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV
2023-12-21 19:16 ` Jeff Law
@ 2023-12-21 22:44 ` 钟居哲
2023-12-23 11:06 ` Li, Pan2
0 siblings, 1 reply; 7+ messages in thread
From: 钟居哲 @ 2023-12-21 22:44 UTC (permalink / raw)
To: Jeff Law, pan2.li, gcc-patches
Cc: yanzhang.wang, kito.cheng, richard.guenther, Tamar Christina
[-- Attachment #1: Type: text/plain, Size: 1302 bytes --]
Maybe use riscv_v ?
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-12-22 03:16
To: pan2.li; gcc-patches
CC: juzhe.zhong; yanzhang.wang; kito.cheng; richard.guenther; tamar.christina
Subject: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV
On 12/20/23 19:25, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to XFail the signbit-5 run test case for
> the RVV. Given the case has one limitation like "This test does not
> work when the truth type does not match vector type." in the beginning
> of the test file. Aka, the RVV vector truth type is not integer type.
>
> The target board of riscv-sim like below will pick up `-march=rv64gcv`
> when building the run test elf. Thus, the RVV cannot bypass this test
> case like aarch64_sve with additional option `-march=armv8-a`.
>
> riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
>
> For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`.
But isn't that just going to turn this into an XPASS when vector is not
enabled?
Looking at a recent rv64gc run of mine:
> PASS: gcc.dg/signbit-5.c (test for excess errors)
> PASS: gcc.dg/signbit-5.c execution test
Ideally we'd find a way to handle with and without vector.
jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV
2023-12-21 22:44 ` 钟居哲
@ 2023-12-23 11:06 ` Li, Pan2
0 siblings, 0 replies; 7+ messages in thread
From: Li, Pan2 @ 2023-12-23 11:06 UTC (permalink / raw)
To: 钟居哲, Jeff Law, gcc-patches
Cc: Wang, Yanzhang, kito.cheng, richard.guenther, Tamar Christina
[-- Attachment #1: Type: text/plain, Size: 2179 bytes --]
Thanks all for comments, will have a try for riscv_v and send V2 if everything goes well.
Pan
From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Friday, December 22, 2023 6:44 AM
To: Jeff Law <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>; richard.guenther <richard.guenther@gmail.com>; Tamar Christina <tamar.christina@arm.com>
Subject: Re: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV
Maybe use riscv_v ?
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Jeff Law<mailto:jeffreyalaw@gmail.com>
Date: 2023-12-22 03:16
To: pan2.li<mailto:pan2.li@intel.com>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>; richard.guenther<mailto:richard.guenther@gmail.com>; tamar.christina<mailto:tamar.christina@arm.com>
Subject: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV
On 12/20/23 19:25, pan2.li@intel.com<mailto:pan2.li@intel.com> wrote:
> From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
>
> This patch would like to XFail the signbit-5 run test case for
> the RVV. Given the case has one limitation like "This test does not
> work when the truth type does not match vector type." in the beginning
> of the test file. Aka, the RVV vector truth type is not integer type.
>
> The target board of riscv-sim like below will pick up `-march=rv64gcv`
> when building the run test elf. Thus, the RVV cannot bypass this test
> case like aarch64_sve with additional option `-march=armv8-a`.
>
> riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
>
> For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`.
But isn't that just going to turn this into an XPASS when vector is not
enabled?
Looking at a recent rv64gc run of mine:
> PASS: gcc.dg/signbit-5.c (test for excess errors)
> PASS: gcc.dg/signbit-5.c execution test
Ideally we'd find a way to handle with and without vector.
jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] RISC-V: XFail the signbit-5 run test for RVV
2023-12-21 2:25 [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV pan2.li
2023-12-21 19:16 ` Jeff Law
@ 2023-12-23 12:39 ` pan2.li
2023-12-23 15:38 ` Jeff Law
1 sibling, 1 reply; 7+ messages in thread
From: pan2.li @ 2023-12-23 12:39 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng,
richard.guenther, jeffreyalaw, tamar.christina
From: Pan Li <pan2.li@intel.com>
This patch would like to XFail the signbit-5 run test case for
the RVV. Given the case has one limitation like "This test does not
work when the truth type does not match vector type." in the beginning
of the test file. Aka, the RVV vector truth type is not integer type.
The target board of riscv-sim like below will pick up `-march=rv64gcv`
when building the run test elf. Thus, the RVV cannot bypass this test
case like aarch64_sve with additional option `-march=armv8-a`.
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`.
The signbit-5.c passed test with below configurations but we need
further investigation for the failures of other configurations.
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
* riscv-sim/-march=rv64imafdcv/-mabi=lp64d/-mcmodel=medlow
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-5.c: XFail for the riscv_v.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.dg/signbit-5.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/signbit-5.c b/gcc/testsuite/gcc.dg/signbit-5.c
index 0fad56c0ea8..1e1b237a0e0 100644
--- a/gcc/testsuite/gcc.dg/signbit-5.c
+++ b/gcc/testsuite/gcc.dg/signbit-5.c
@@ -5,6 +5,7 @@
/* { dg-additional-options "-mno-avx512f" { target { i?86-*-* x86_64-*-* } } } */
/* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */
/* { dg-xfail-run-if "truth type does not match vector type" { amdgcn-*-* } } */
+/* { dg-xfail-run-if "truth type does not match vector type" { riscv_v } } */
#include <stdint.h>
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2] RISC-V: XFail the signbit-5 run test for RVV
2023-12-23 12:39 ` [PATCH v2] " pan2.li
@ 2023-12-23 15:38 ` Jeff Law
2023-12-24 1:50 ` Li, Pan2
0 siblings, 1 reply; 7+ messages in thread
From: Jeff Law @ 2023-12-23 15:38 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: juzhe.zhong, yanzhang.wang, kito.cheng, richard.guenther,
tamar.christina
On 12/23/23 05:39, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to XFail the signbit-5 run test case for
> the RVV. Given the case has one limitation like "This test does not
> work when the truth type does not match vector type." in the beginning
> of the test file. Aka, the RVV vector truth type is not integer type.
>
> The target board of riscv-sim like below will pick up `-march=rv64gcv`
> when building the run test elf. Thus, the RVV cannot bypass this test
> case like aarch64_sve with additional option `-march=armv8-a`.
>
> riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
>
> For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`.
>
> The signbit-5.c passed test with below configurations but we need
> further investigation for the failures of other configurations.
>
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64imafdcv/-mabi=lp64d/-mcmodel=medlow
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/signbit-5.c: XFail for the riscv_v.
OK
jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v2] RISC-V: XFail the signbit-5 run test for RVV
2023-12-23 15:38 ` Jeff Law
@ 2023-12-24 1:50 ` Li, Pan2
0 siblings, 0 replies; 7+ messages in thread
From: Li, Pan2 @ 2023-12-24 1:50 UTC (permalink / raw)
To: Jeff Law, gcc-patches
Cc: juzhe.zhong, Wang, Yanzhang, kito.cheng, richard.guenther,
tamar.christina
Committed, thanks Jeff.
Pan
-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com>
Sent: Saturday, December 23, 2023 11:38 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; richard.guenther@gmail.com; tamar.christina@arm.com
Subject: Re: [PATCH v2] RISC-V: XFail the signbit-5 run test for RVV
On 12/23/23 05:39, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to XFail the signbit-5 run test case for
> the RVV. Given the case has one limitation like "This test does not
> work when the truth type does not match vector type." in the beginning
> of the test file. Aka, the RVV vector truth type is not integer type.
>
> The target board of riscv-sim like below will pick up `-march=rv64gcv`
> when building the run test elf. Thus, the RVV cannot bypass this test
> case like aarch64_sve with additional option `-march=armv8-a`.
>
> riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
>
> For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`.
>
> The signbit-5.c passed test with below configurations but we need
> further investigation for the failures of other configurations.
>
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl1024b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
> * riscv-sim/-march=rv64imafdcv/-mabi=lp64d/-mcmodel=medlow
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/signbit-5.c: XFail for the riscv_v.
OK
jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-12-24 1:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2023-12-21 2:25 [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV pan2.li
2023-12-21 19:16 ` Jeff Law
2023-12-21 22:44 ` 钟居哲
2023-12-23 11:06 ` Li, Pan2
2023-12-23 12:39 ` [PATCH v2] " pan2.li
2023-12-23 15:38 ` Jeff Law
2023-12-24 1:50 ` Li, Pan2
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