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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id u7-20020a17090341c700b001872999f58esm8037057ple.189.2022.11.14.13.23.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Nov 2022 13:23:38 -0800 (PST) Message-ID: <9161a76a-4181-e5f9-620e-c1c1195c9954@gmail.com> Date: Mon, 14 Nov 2022 14:23:37 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion Content-Language: en-US To: Palmer Dabbelt , philipp.tomsich@vrull.eu Cc: gcc-patches@gcc.gnu.org, Vineet Gupta , jlaw@ventanamicro.com, Kito Cheng , christoph.muellner@vrull.eu References: From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/14/22 13:00, Palmer Dabbelt wrote: > On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.tomsich@vrull.eu wrote: >> >> This series provides support for the Ventana VT1 (a 4-way superscalar >> rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support >> for the supported instruction fusion patterns. >> >> This includes the addition of the fusion-aware scheduling >> infrastructure for RISC-V and implements idiom recognition for the >> fusion patterns supported by VT1. >> >> Note that we don't signal support for XVentanaCondOps at this point, >> as the XVentanaCondOps support is in-flight separately. Changing the >> defaults for VT1 can happen late in the cycle, so no need to link the >> two different changesets. >> >> Changes in v2: >> - Rebased and changed over to .rst-based documentation >> - Updated to catch more fusion cases >> - Signals support for Zifencei >> >> Philipp Tomsich (2): >>   RISC-V: Add basic support for the Ventana-VT1 core >>   RISC-V: Add instruction fusion (for ventana-vt1) >> >>  gcc/config/riscv/riscv-cores.def              |   3 + >>  gcc/config/riscv/riscv-opts.h                 |   2 +- >>  gcc/config/riscv/riscv.cc                     | 233 ++++++++++++++++++ >>  .../risc-v-options.rst                        |   5 +- >>  4 files changed, 240 insertions(+), 3 deletions(-) > > I guess we never really properly talked about this on the GCC mailing > lists, but IMO it's fine to start taking code for designs that have > been announced under the assumption that if the hardware doesn't > actually show up according to those timelines that it will be assumed > to have never existed and thus be removed more quickly than usual. Absolutely.   I have zero interest in carrying around code for nonexistent or dead variants. > > That said, I can't find anything describing that the VT-1 exists aside > from these patches.  Is there anything that describes this design and > when it's expected to be available? What do you need?  I can give some broad overview information on the design, but it would likely just mirror what's already been mentioned in these patches. As far as schedules.  I'm not sure what I can say.  I'll check on that. It was never my intention to bypass any process/procedures here. So if I did, my apologies. jeff