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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id g9-20020a63f409000000b005035f5e1f9csm1862807pgi.2.2023.03.14.10.59.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Mar 2023 10:59:16 -0700 (PDT) Message-ID: <9182aed0-3376-d904-087b-670d383c3769@gmail.com> Date: Tue, 14 Mar 2023 11:59:15 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH] RISC-V: Fine tune RA constraint for narrow instructions Content-Language: en-US To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com References: <20230310030205.90760-1-juzhe.zhong@rivai.ai> From: Jeff Law In-Reply-To: <20230310030205.90760-1-juzhe.zhong@rivai.ai> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 3/9/23 20:02, juzhe.zhong@rivai.ai wrote: > From: Ju-Zhe Zhong > > According to RVV ISA, for narrow instructions: > > The destination EEW is smaller than the source EEW and the overlap is > in the lowest-numbered part of the source register group. > (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not). > > We should allow narrow instructions partially overlap base on the rule of RVV ISA above > so that we could exploit the useage of vector registers. > > Consider these cases: > https://godbolt.org/z/o6sc4eqGj > > some cases in LLVM have redundant move instructions, > some cases in LLVM have redundant register spillings. > > Now after this patch, GCC can have perfect RA && codegen for different pressure RA cases. > > gcc/ChangeLog: > > * config/riscv/vector.md: Fine tune RA constraints. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/narrow_constraint-1.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-10.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-11.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-2.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-3.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-4.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-5.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-6.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-7.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-8.c: New test. > * gcc.target/riscv/rvv/base/narrow_constraint-9.c: New test. ISTM this should wait for gcc-14. Yea, the risk is low and limited to RVV, but it seems to fall outside the basic intrinsic support we agreed to allow into gcc-13 post-feature-freeze. Comments? Jeff