From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-fw-80006.amazon.com (smtp-fw-80006.amazon.com [99.78.197.217]) by sourceware.org (Postfix) with ESMTPS id 68B453839D26 for ; Wed, 7 Dec 2022 00:51:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 68B453839D26 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=amazon.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1670374297; x=1701910297; h=from:to:cc:date:message-id:references:in-reply-to: mime-version:subject; bh=xMnivZZfgZBxmbmxWfJAqA4ZoSsY8OXUa82gjjsOmZw=; b=PTenX4uUzy+YEQtODvC43pa0gDsKT+/77K+pWQZh/hW19y0LdTW3XpnD fIzXJypEasFNe/zkgGsNPpSJKw2GIQvtS2x/ScAQ5Jn5TP6420uH7UK8G hO6KZeRV5+3gGOXnJvF8q0VJ9PUDO9/meXnoTmj0oyAGGoI4ggUWxn3Ag U=; X-Amazon-filename: 0001-AArch64-Add-UNSPECV_PATCHABLE_AREA-PR98776.patch X-IronPort-AV: E=Sophos;i="5.96,223,1665446400"; d="scan'208,217,223";a="158626001" Subject: Re: AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776] Thread-Topic: AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776] Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO email-inbound-relay-iad-1d-m6i4x-d23e07e8.us-east-1.amazon.com) ([10.25.36.210]) by smtp-border-fw-80006.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 00:51:35 +0000 Received: from EX13MTAUWC002.ant.amazon.com (iad12-ws-svc-p26-lb9-vlan3.iad.amazon.com [10.40.163.38]) by email-inbound-relay-iad-1d-m6i4x-d23e07e8.us-east-1.amazon.com (Postfix) with ESMTPS id 2C6EA8030B; Wed, 7 Dec 2022 00:51:32 +0000 (UTC) Received: from EX19D001UWB001.ant.amazon.com (10.13.138.18) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 7 Dec 2022 00:51:32 +0000 Received: from EX19D001UWB002.ant.amazon.com (10.13.138.54) by EX19D001UWB001.ant.amazon.com (10.13.138.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1118.20; Wed, 7 Dec 2022 00:51:32 +0000 Received: from EX19D001UWB002.ant.amazon.com ([fe80::228:5f96:8949:28b8]) by EX19D001UWB002.ant.amazon.com ([fe80::228:5f96:8949:28b8%7]) with mapi id 15.02.1118.020; Wed, 7 Dec 2022 00:51:32 +0000 From: "Pop, Sebastian" To: Richard Sandiford CC: "gcc-patches@gcc.gnu.org" , "sebpop@gmail.com" , Kyrylo Tkachov Thread-Index: AQHZBTCTBfQC3+DIFk6eavlOh3NJy65fMORUgAJJ8SU= Date: Wed, 7 Dec 2022 00:51:32 +0000 Message-ID: <91a2310b642145aa9039066951a5f571@amazon.com> References: <3b2be13be3534681af5a64b8163a3c8c@amazon.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.43.160.83] Content-Type: multipart/mixed; boundary="_004_91a2310b642145aa9039066951a5f571amazoncom_" MIME-Version: 1.0 X-Spam-Status: No, score=-18.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --_004_91a2310b642145aa9039066951a5f571amazoncom_ Content-Type: multipart/alternative; boundary="_000_91a2310b642145aa9039066951a5f571amazoncom_" --_000_91a2310b642145aa9039066951a5f571amazoncom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Thanks Richard for your review and for pointing out the issue with BTI. The current patch removes the existing BTI instruction, and then adds the BTI hint when expanding the patchable_area pseudo. The attached patch passed bootstrap and regression test on arm64-linux. Ok to commit to gcc trunk? Thank you, Sebastian ________________________________ From: Richard Sandiford Sent: Monday, December 5, 2022 5:34:40 AM To: Pop, Sebastian Cc: gcc-patches@gcc.gnu.org; sebpop@gmail.com; Kyrylo Tkachov Subject: RE: [EXTERNAL]AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776] CAUTION: This email originated from outside of the organization. Do not cli= ck links or open attachments unless you can confirm the sender and know the= content is safe. "Pop, Sebastian" writes: > Hi, > > Currently patchable area is at the wrong place on AArch64. It is placed > immediately after function label, before .cfi_startproc. This patch > adds UNSPECV_PATCHABLE_AREA for pseudo patchable area instruction and > modifies aarch64_print_patchable_function_entry to avoid placing > patchable area before .cfi_startproc. > > The patch passed bootstrap and regression test on aarch64-linux. > Ok to commit to trunk and backport to active release branches? Looks good, but doesn't the problem described in the PR then still apply to the BTI emitted by: if (cfun->machine->label_is_assembled && aarch64_bti_enabled () && !cgraph_node::get (cfun->decl)->only_called_directly_p ()) { /* Remove the BTI that follows the patch area and insert a new BTI before the patch area right after the function label. */ rtx_insn *insn =3D next_real_nondebug_insn (get_insns ()); if (insn && INSN_P (insn) && GET_CODE (PATTERN (insn)) =3D=3D UNSPEC_VOLATILE && XINT (PATTERN (insn), 1) =3D=3D UNSPECV_BTI_C) delete_insn (insn); asm_fprintf (file, "\thint\t34 // bti c\n"); } ? It seems like the BTI will be before the cfi_startproc and the patchable entry afterwards. I guess we should keep the BTI instruction as-is (rather than printing a .hint) and emit the new UNSPECV_PATCHABLE_AREA after the BTI rather than before it. Thanks, Richard > Thanks, > Sebastian > > gcc/ > PR target/93492 > * config/aarch64/aarch64-protos.h (aarch64_output_patchable_area): > Declared. > * config/aarch64/aarch64.cc (aarch64_print_patchable_function_ent= ry): > Emit an UNSPECV_PATCHABLE_AREA pseudo instruction. > (aarch64_output_patchable_area): New. > * config/aarch64/aarch64.md (UNSPECV_PATCHABLE_AREA): New. > (patchable_area): Define. > > gcc/testsuite/ > PR target/93492 > * gcc.target/aarch64/pr98776.c: New. > > > From b9cf87bcdf65f515b38f1851eb95c18aaa180253 Mon Sep 17 00:00:00 2001 > From: Sebastian Pop > Date: Wed, 30 Nov 2022 19:45:24 +0000 > Subject: [PATCH] AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776] > > Currently patchable area is at the wrong place on AArch64. It is placed > immediately after function label, before .cfi_startproc. This patch > adds UNSPECV_PATCHABLE_AREA for pseudo patchable area instruction and > modifies aarch64_print_patchable_function_entry to avoid placing > patchable area before .cfi_startproc. > > gcc/ > PR target/93492 > * config/aarch64/aarch64-protos.h (aarch64_output_patchable_area): > Declared. > * config/aarch64/aarch64.cc (aarch64_print_patchable_function_entry= ): > Emit an UNSPECV_PATCHABLE_AREA pseudo instruction. > (aarch64_output_patchable_area): New. > * config/aarch64/aarch64.md (UNSPECV_PATCHABLE_AREA): New. > (patchable_area): Define. > > gcc/testsuite/ > PR target/93492 > * gcc.target/aarch64/pr98776.c: New. > --- > gcc/config/aarch64/aarch64-protos.h | 2 ++ > gcc/config/aarch64/aarch64.cc | 24 +++++++++++++++++++++- > gcc/config/aarch64/aarch64.md | 14 +++++++++++++ > gcc/testsuite/gcc.target/aarch64/pr98776.c | 11 ++++++++++ > 4 files changed, 50 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/aarch64/pr98776.c > > diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aar= ch64-protos.h > index 4be93c93c26..2fba24d947d 100644 > --- a/gcc/config/aarch64/aarch64-protos.h > +++ b/gcc/config/aarch64/aarch64-protos.h > @@ -1074,4 +1074,6 @@ const char *aarch64_indirect_call_asm (rtx); > extern bool aarch64_harden_sls_retbr_p (void); > extern bool aarch64_harden_sls_blr_p (void); > > +extern void aarch64_output_patchable_area (unsigned int, bool); > + > #endif /* GCC_AARCH64_PROTOS_H */ > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > index e97f3b32f7c..e84b33b958c 100644 > --- a/gcc/config/aarch64/aarch64.cc > +++ b/gcc/config/aarch64/aarch64.cc > @@ -22684,7 +22684,29 @@ aarch64_print_patchable_function_entry (FILE *fi= le, > asm_fprintf (file, "\thint\t34 // bti c\n"); > } > > - default_print_patchable_function_entry (file, patch_area_size, record_= p); > + if (cfun->machine->label_is_assembled) > + { > + rtx pa =3D gen_patchable_area (GEN_INT (patch_area_size), > + GEN_INT (record_p)); > + basic_block bb =3D ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb; > + rtx_insn *insn =3D emit_insn_before (pa, BB_HEAD (bb)); > + INSN_ADDRESSES_NEW (insn, -1); > + } > + else > + { > + default_print_patchable_function_entry (file, patch_area_size, > + record_p); > + } > +} > + > +/* Output patchable area. */ > + > +void > +aarch64_output_patchable_area (unsigned int patch_area_size, bool record= _p) > +{ > + default_print_patchable_function_entry (asm_out_file, > + patch_area_size, > + record_p); > } > > /* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases= . */ > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 76b6898ca04..6501503eb25 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -303,6 +303,7 @@ > UNSPEC_TAG_SPACE ; Translate address to MTE tag address spac= e. > UNSPEC_LD1RO > UNSPEC_SALT_ADDR > + UNSPECV_PATCHABLE_AREA > ]) > > (define_c_enum "unspecv" [ > @@ -7821,6 +7822,19 @@ > [(set_attr "type" "ls64")] > ) > > +(define_insn "patchable_area" > + [(unspec_volatile [(match_operand 0 "const_int_operand") > + (match_operand 1 "const_int_operand")] > + UNSPECV_PATCHABLE_AREA)] > + "" > +{ > + aarch64_output_patchable_area (INTVAL (operands[0]), > + INTVAL (operands[1]) !=3D 0); > + return ""; > +} > + [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))] > +) > + > ;; AdvSIMD Stuff > (include "aarch64-simd.md") > > diff --git a/gcc/testsuite/gcc.target/aarch64/pr98776.c b/gcc/testsuite/g= cc.target/aarch64/pr98776.c > new file mode 100644 > index 00000000000..b075b8f75ef > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/pr98776.c > @@ -0,0 +1,11 @@ > +/* { dg-do "compile" } */ > +/* { dg-options "-O1 -fpatchable-function-entry=3D1 -fasynchronous-unwin= d-tables" } */ > + > +/* Test the placement of the .LPFE0 label. */ > + > +void > +foo (void) > +{ > +} > + > +/* { dg-final { scan-assembler "\t\.cfi_startproc\n.*\.LPFE0:\n\tnop\n\t= ret\n" } } */ --_000_91a2310b642145aa9039066951a5f571amazoncom_-- --_004_91a2310b642145aa9039066951a5f571amazoncom_ Content-Type: text/x-patch; name="0001-AArch64-Add-UNSPECV_PATCHABLE_AREA-PR98776.patch" Content-Description: 0001-AArch64-Add-UNSPECV_PATCHABLE_AREA-PR98776.patch Content-Disposition: attachment; filename="0001-AArch64-Add-UNSPECV_PATCHABLE_AREA-PR98776.patch"; size=7319; creation-date="Wed, 07 Dec 2022 00:48:47 GMT"; modification-date="Wed, 07 Dec 2022 00:48:47 GMT" Content-Transfer-Encoding: base64 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