[PATCH 0/3] rs6000: Delete <Ff> and <Fv>

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* [PATCH 0/3] rs6000: Delete <Ff> and <Fv>
@ 2022-05-11 14:57 Segher Boessenkool
  2022-05-11 14:57 ` [PATCH 1/3] rs6000: Delete RS6000_CONSTRAINT_f Segher Boessenkool
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Segher Boessenkool @ 2022-05-11 14:57 UTC (permalink / raw)
  To: gcc-patches; +Cc: dje.gcc, Kewen.Lin, Segher Boessenkool

Since 2c2aa74d1dft ("rs6000: Remove Xilinx FP") constraints d and f mean
exactly the same thing, so we can use "d" always.  This series cleans up
the constraint initialisation a bit, and removes the <Ff> mode
attribute, since it can now always be "d".  It also removes <Fv> since it
always is "wa", and it simplifies things nicely now that we can also
delete <Ff>.

Tested on powerpc64-linux {-m32,-m64}.  Committing to trunk.

Segher

Segher Boessenkool (3):
  rs6000: Delete RS6000_CONSTRAINT_f
  rs6000: Remove <Ff>
  rs6000: Remove <Fv>

 gcc/config/rs6000/constraints.md |   2 +-
 gcc/config/rs6000/rs6000.cc      |  16 +---
 gcc/config/rs6000/rs6000.h       |   3 +-
 gcc/config/rs6000/rs6000.md      | 177 +++++++++++++++++++--------------------
 4 files changed, 89 insertions(+), 109 deletions(-)

-- 
1.8.3.1

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 1/3] rs6000: Delete RS6000_CONSTRAINT_f
  2022-05-11 14:57 [PATCH 0/3] rs6000: Delete <Ff> and <Fv> Segher Boessenkool
@ 2022-05-11 14:57 ` Segher Boessenkool
  2022-05-11 14:57 ` [PATCH 2/3] rs6000: Remove <Ff> Segher Boessenkool
  2022-05-11 14:57 ` [PATCH 3/3] rs6000: Remove <Fv> Segher Boessenkool
  2 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2022-05-11 14:57 UTC (permalink / raw)
  To: gcc-patches; +Cc: dje.gcc, Kewen.Lin, Segher Boessenkool

Constraint "f" is always exactly the same as constraint "d", so we do
not need RS6000_CONSTRAINT_f.

2022-05-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/constraints.md (register_constraint "f"): Use
	RS6000_CONSTRAINT_d.
	* config/rs6000/rs6000.cc (rs6000_debug_reg_global): Do not handle
	RS6000_CONSTRAINT_f.
	(rs6000_init_hard_regno_mode_ok): Ditto.  Reorder and simplify a bit.
	* config/rs6000/rs6000.h (r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_d.

---
 gcc/config/rs6000/constraints.md |  2 +-
 gcc/config/rs6000/rs6000.cc      | 16 +++-------------
 gcc/config/rs6000/rs6000.h       |  3 +--
 3 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 7aaffd9f9a89..00ac4b86c058 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -29,7 +29,7 @@ (define_register_constraint "b" "BASE_REGS"
   "A base register.  Like @code{r}, but @code{r0} is not allowed, so
    @code{r1}@dots{}@code{r31}.")
 
-(define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]"
+(define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_d]"
   "A floating point register (FPR), @code{f0}@dots{}@code{f31}.")
 
 (define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]"
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4030864aa1af..5cb8a53e9ce6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2305,7 +2305,6 @@ rs6000_debug_reg_global (void)
   fprintf (stderr,
 	   "\n"
 	   "d  reg_class = %s\n"
-	   "f  reg_class = %s\n"
 	   "v  reg_class = %s\n"
 	   "wa reg_class = %s\n"
 	   "we reg_class = %s\n"
@@ -2314,7 +2313,6 @@ rs6000_debug_reg_global (void)
 	   "wA reg_class = %s\n"
 	   "\n",
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
@@ -2953,7 +2951,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
      constraints are:
 
 	d  - Register class to use with traditional DFmode instructions.
-	f  - Register class to use with traditional SFmode instructions.
 	v  - Altivec register.
 	wa - Any VSX register.
 	wc - Reserved to represent individual CR bits (used in LLVM).
@@ -2962,18 +2959,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 	wx - Float register if we can do 32-bit int stores.  */
 
   if (TARGET_HARD_FLOAT)
-    {
-      rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;	/* SFmode  */
-      rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;	/* DFmode  */
-    }
-
-  if (TARGET_VSX)
-    rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
-
-  /* Add conditional constraints based on various options, to allow us to
-     collapse multiple insn patterns.  */
+    rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
   if (TARGET_ALTIVEC)
     rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
+  if (TARGET_VSX)
+    rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
 
   if (TARGET_POWERPC64)
     {
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 523256a5c9d5..20b9d11424db 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1240,8 +1240,7 @@ extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
 /* Register classes for various constraints that are based on the target
    switches.  */
 enum r6000_reg_class_enum {
-  RS6000_CONSTRAINT_d,		/* fpr registers for double values */
-  RS6000_CONSTRAINT_f,		/* fpr registers for single values */
+  RS6000_CONSTRAINT_d,		/* FPR registers */
   RS6000_CONSTRAINT_v,		/* Altivec registers */
   RS6000_CONSTRAINT_wa,		/* Any VSX register */
   RS6000_CONSTRAINT_we,		/* VSX register if ISA 3.0 vector. */
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 2/3] rs6000: Remove <Ff>
  2022-05-11 14:57 [PATCH 0/3] rs6000: Delete <Ff> and <Fv> Segher Boessenkool
  2022-05-11 14:57 ` [PATCH 1/3] rs6000: Delete RS6000_CONSTRAINT_f Segher Boessenkool
@ 2022-05-11 14:57 ` Segher Boessenkool
  2022-05-11 14:57 ` [PATCH 3/3] rs6000: Remove <Fv> Segher Boessenkool
  2 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2022-05-11 14:57 UTC (permalink / raw)
  To: gcc-patches; +Cc: dje.gcc, Kewen.Lin, Segher Boessenkool

The <Ff> mode iterator can just use "d" always.

2022-05-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md: Use d instead of <Ff>.

---
 gcc/config/rs6000/rs6000.md | 117 +++++++++++++++++++++-----------------------
 1 file changed, 57 insertions(+), 60 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 64049a6e521c..0100d67e9217 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -622,9 +622,6 @@ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
 ; Iterator for ISA 3.0 supported floating point types
 (define_mode_iterator FP_ISA3 [SF DF])
 
-; SF/DF constraint for arithmetic on traditional floating point registers
-(define_mode_attr Ff		[(SF "f") (DF "d") (DI "d")])
-
 ; SF/DF constraint for arithmetic on VSX registers using instructions added in
 ; ISA 2.06 (power7).  This includes instructions that normally target DF mode,
 ; but are used on SFmode, since internally SFmode values are kept in the DFmode
@@ -4871,8 +4868,8 @@ (define_expand "abs<mode>2"
   "")
 
 (define_insn "*abs<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-	(abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+	(abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
   "TARGET_HARD_FLOAT"
   "@
    fabs %0,%1
@@ -4880,10 +4877,10 @@ (define_insn "*abs<mode>2_fpr"
   [(set_attr "type" "fpsimple")])
 
 (define_insn "*nabs<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
 	(neg:SFDF
 	 (abs:SFDF
-	  (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
+	  (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))))]
   "TARGET_HARD_FLOAT"
   "@
    fnabs %0,%1
@@ -4897,8 +4894,8 @@ (define_expand "neg<mode>2"
   "")
 
 (define_insn "*neg<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-	(neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+	(neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
   "TARGET_HARD_FLOAT"
   "@
    fneg %0,%1
@@ -4913,9 +4910,9 @@ (define_expand "add<mode>3"
   "")
 
 (define_insn "*add<mode>3_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
-	(plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa")
-		   (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa")
+		   (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fadd<s> %0,%1,%2
@@ -4931,9 +4928,9 @@ (define_expand "sub<mode>3"
   "")
 
 (define_insn "*sub<mode>3_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
-	(minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
-		    (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+		    (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fsub<s> %0,%1,%2
@@ -4949,9 +4946,9 @@ (define_expand "mul<mode>3"
   "")
 
 (define_insn "*mul<mode>3_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
-	(mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa")
-		   (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa")
+		   (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fmul<s> %0,%1,%2
@@ -4975,9 +4972,9 @@ (define_expand "div<mode>3"
 })
 
 (define_insn "*div<mode>3_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
-	(div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
-		  (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+		  (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fdiv<s> %0,%1,%2
@@ -4986,8 +4983,8 @@ (define_insn "*div<mode>3_fpr"
    (set_attr "isa" "*,<Fisa>")])
 
 (define_insn "*sqrt<mode>2_internal"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
-	(sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
   "@
    fsqrt<s> %0,%1
@@ -5014,8 +5011,8 @@ (define_expand "sqrt<mode>2"
 
 ;; Floating point reciprocal approximation
 (define_insn "fre<sd>"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRES))]
   "TARGET_<FFRE>"
   "@
@@ -5061,8 +5058,8 @@ (define_expand "remainder<mode>3"
  })
 
 (define_insn "*rsqrt<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_RSQRT))]
   "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
   "@
@@ -5074,8 +5071,8 @@ (define_insn "*rsqrt<mode>2"
 ;; Floating point comparisons
 (define_insn "*cmp<mode>_fpr"
   [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
-	(compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
-		      (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+	(compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+		      (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fcmpu %0,%1,%2
@@ -5277,9 +5274,9 @@ (define_expand "copysign<mode>3"
 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
 ;; compiler from optimizing -0.0
 (define_insn "copysign<mode>3_fcpsgn"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
-		      (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")
+		      (match_operand:SFDF 2 "gpc_reg_operand" "d,<Fv>")]
 		     UNSPEC_COPYSIGN))]
   "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
   "@
@@ -6205,7 +6202,7 @@ (define_expand "fix_trunc<mode>di2"
 
 (define_insn "*fix_trunc<mode>di2_fctidz"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
-	(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+	(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
   "TARGET_HARD_FLOAT && TARGET_FCFID"
   "@
    fctidz %0,%1
@@ -6324,7 +6321,7 @@ (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
 
 (define_insn "fixuns_trunc<mode>di2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
-	(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+	(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
   "TARGET_HARD_FLOAT && TARGET_FCTIDUZ"
   "@
    fctiduz %0,%1
@@ -6474,7 +6471,7 @@ (define_expand "rs6000_set_fpscr_drn"
 (define_insn "fctiwz_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
 	(unspec:DI [(fix:SI
-		     (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
+		     (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))]
 		   UNSPEC_FCTIWZ))]
   "TARGET_HARD_FLOAT"
   "@
@@ -6485,7 +6482,7 @@ (define_insn "fctiwz_<mode>"
 (define_insn "fctiwuz_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
 	(unspec:DI [(unsigned_fix:SI
-		     (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
+		     (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))]
 		   UNSPEC_FCTIWUZ))]
   "TARGET_HARD_FLOAT && TARGET_FCTIWUZ"
   "@
@@ -6588,8 +6585,8 @@ (define_insn "lrint<mode>di2"
   [(set_attr "type" "fp")])
 
 (define_insn "btrunc<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
 		     UNSPEC_FRIZ))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -6598,8 +6595,8 @@ (define_insn "btrunc<mode>2"
   [(set_attr "type" "fp")])
 
 (define_insn "ceil<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
 		     UNSPEC_FRIP))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -6608,8 +6605,8 @@ (define_insn "ceil<mode>2"
   [(set_attr "type" "fp")])
 
 (define_insn "floor<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
 		     UNSPEC_FRIM))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -10152,7 +10149,7 @@ (define_insn "*movqi_update3"
    (set_attr "indexed" "yes,no")])
 
 (define_insn "*mov<SFDF:mode>_update1"
-  [(set (match_operand:SFDF 3 "gpc_reg_operand" "=<SFDF:Ff>,<SFDF:Ff>")
+  [(set (match_operand:SFDF 3 "gpc_reg_operand" "=d,d")
 	(mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
 			  (match_operand:P 2 "reg_or_short_operand" "r,I"))))
    (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
@@ -10171,7 +10168,7 @@ (define_insn "*mov<SFDF:mode>_update1"
 (define_insn "*mov<SFDF:mode>_update2"
   [(set (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
 			  (match_operand:P 2 "reg_or_short_operand" "r,I")))
-	(match_operand:SFDF 3 "gpc_reg_operand" "<SFDF:Ff>,<SFDF:Ff>"))
+	(match_operand:SFDF 3 "gpc_reg_operand" "d,d"))
    (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
 	(plus:P (match_dup 1) (match_dup 2)))]
   "TARGET_HARD_FLOAT && TARGET_UPDATE
@@ -14142,11 +14139,11 @@ (define_expand "fma<mode>4"
   "")
 
 (define_insn "*fma<mode>4_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa")
 	(fma:SFDF
-	  (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa,wa")
-	  (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
-	  (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))]
+	  (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa,wa")
+	  (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0")
+	  (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fmadd<s> %0,%1,%2,%3
@@ -14166,11 +14163,11 @@ (define_expand "fms<mode>4"
   "")
 
 (define_insn "*fms<mode>4_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa")
 	(fma:SFDF
-	 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
-	 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
-	 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
+	 (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa")
+	 (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0")
+	 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa"))))]
   "TARGET_HARD_FLOAT"
   "@
    fmsub<s> %0,%1,%2,%3
@@ -14213,12 +14210,12 @@ (define_expand "nfma<mode>4"
   "")
 
 (define_insn "*nfma<mode>4_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa")
 	(neg:SFDF
 	 (fma:SFDF
-	  (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
-	  (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
-	  (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
+	  (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa")
+	  (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0")
+	  (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa"))))]
   "TARGET_HARD_FLOAT"
   "@
    fnmadd<s> %0,%1,%2,%3
@@ -14239,13 +14236,13 @@ (define_expand "nfms<mode>4"
   "")
 
 (define_insn "*nfmssf4_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa")
 	(neg:SFDF
 	 (fma:SFDF
-	  (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
-	  (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
+	  (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa")
+	  (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0")
 	  (neg:SFDF
-	   (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))))]
+	   (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa")))))]
   "TARGET_HARD_FLOAT"
   "@
    fnmsub<s> %0,%1,%2,%3
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 3/3] rs6000: Remove <Fv>
  2022-05-11 14:57 [PATCH 0/3] rs6000: Delete <Ff> and <Fv> Segher Boessenkool
  2022-05-11 14:57 ` [PATCH 1/3] rs6000: Delete RS6000_CONSTRAINT_f Segher Boessenkool
  2022-05-11 14:57 ` [PATCH 2/3] rs6000: Remove <Ff> Segher Boessenkool
@ 2022-05-11 14:57 ` Segher Boessenkool
  2 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2022-05-11 14:57 UTC (permalink / raw)
  To: gcc-patches; +Cc: dje.gcc, Kewen.Lin, Segher Boessenkool

The <Fv> mode iterator always expands to "wa".

2022-05-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md: Use wa instead of <Fv>.

---
 gcc/config/rs6000/rs6000.md | 98 +++++++++++++++++++++------------------------
 1 file changed, 46 insertions(+), 52 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0100d67e9217..bf85baa53702 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -622,12 +622,6 @@ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
 ; Iterator for ISA 3.0 supported floating point types
 (define_mode_iterator FP_ISA3 [SF DF])
 
-; SF/DF constraint for arithmetic on VSX registers using instructions added in
-; ISA 2.06 (power7).  This includes instructions that normally target DF mode,
-; but are used on SFmode, since internally SFmode values are kept in the DFmode
-; format.
-(define_mode_attr Fv		[(SF "wa") (DF "wa") (DI "wa")])
-
 ; Which isa is needed for those float instructions?
 (define_mode_attr Fisa		[(SF "p8v")  (DF "*") (DI "*")])
 
@@ -4868,8 +4862,8 @@ (define_expand "abs<mode>2"
   "")
 
 (define_insn "*abs<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fabs %0,%1
@@ -4877,10 +4871,10 @@ (define_insn "*abs<mode>2_fpr"
   [(set_attr "type" "fpsimple")])
 
 (define_insn "*nabs<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(neg:SFDF
 	 (abs:SFDF
-	  (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))))]
+	  (match_operand:SFDF 1 "gpc_reg_operand" "d,wa"))))]
   "TARGET_HARD_FLOAT"
   "@
    fnabs %0,%1
@@ -4894,8 +4888,8 @@ (define_expand "neg<mode>2"
   "")
 
 (define_insn "*neg<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fneg %0,%1
@@ -5274,9 +5268,9 @@ (define_expand "copysign<mode>3"
 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
 ;; compiler from optimizing -0.0
 (define_insn "copysign<mode>3_fcpsgn"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")
-		      (match_operand:SFDF 2 "gpc_reg_operand" "d,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+		      (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_COPYSIGN))]
   "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
   "@
@@ -5308,9 +5302,9 @@ (define_expand "s<minmax><mode>3"
 })
 
 (define_insn "*s<minmax><mode>3_vsx"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
-	(fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "<Fv>")
-			(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")))]
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa")
+	(fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "wa")
+			(match_operand:SFDF 2 "vsx_register_operand" "wa")))]
   "TARGET_VSX && TARGET_HARD_FLOAT"
 {
   return (TARGET_P9_MINMAX
@@ -5465,13 +5459,13 @@ (define_insn "*fsel<SFDF:mode><SFDF2:mode>4"
   [(set_attr "type" "fp")])
 
 (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=&wa,wa")
 	(if_then_else:SFDF
 	 (match_operator:CCFP 1 "fpmask_comparison_operator"
-		[(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
-		 (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
-	 (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
-	 (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
+		[(match_operand:SFDF2 2 "vsx_register_operand" "wa,wa")
+		 (match_operand:SFDF2 3 "vsx_register_operand" "wa,wa")])
+	 (match_operand:SFDF 4 "vsx_register_operand" "wa,wa")
+	 (match_operand:SFDF 5 "vsx_register_operand" "wa,wa")))
    (clobber (match_scratch:V2DI 6 "=0,&wa"))]
   "TARGET_P9_MINMAX"
   "#"
@@ -5497,13 +5491,13 @@ (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
 
 ;; Handle inverting the fpmask comparisons.
 (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_invert_p9"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=&wa,wa")
 	(if_then_else:SFDF
 	 (match_operator:CCFP 1 "invert_fpmask_comparison_operator"
-		[(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
-		 (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
-	 (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
-	 (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
+		[(match_operand:SFDF2 2 "vsx_register_operand" "wa,wa")
+		 (match_operand:SFDF2 3 "vsx_register_operand" "wa,wa")])
+	 (match_operand:SFDF 4 "vsx_register_operand" "wa,wa")
+	 (match_operand:SFDF 5 "vsx_register_operand" "wa,wa")))
    (clobber (match_scratch:V2DI 6 "=0,&wa"))]
   "TARGET_P9_MINMAX"
   "#"
@@ -5536,8 +5530,8 @@ (define_insn "*fpmask<mode>"
   [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
 	(if_then_else:V2DI
 	 (match_operator:CCFP 1 "fpmask_comparison_operator"
-		[(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")
-		 (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")])
+		[(match_operand:SFDF 2 "vsx_register_operand" "wa")
+		 (match_operand:SFDF 3 "vsx_register_operand" "wa")])
 	 (match_operand:V2DI 4 "all_ones_constant" "")
 	 (match_operand:V2DI 5 "zero_constant" "")))]
   "TARGET_P9_MINMAX"
@@ -5545,11 +5539,11 @@ (define_insn "*fpmask<mode>"
   [(set_attr "type" "fpcompare")])
 
 (define_insn "*xxsel<mode>"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa")
 	(if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
 			       (match_operand:V2DI 2 "zero_constant" ""))
-			   (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")
-			   (match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
+			   (match_operand:SFDF 3 "vsx_register_operand" "wa")
+			   (match_operand:SFDF 4 "vsx_register_operand" "wa")))]
   "TARGET_P9_MINMAX"
   "xxsel %x0,%x4,%x3,%x1"
   [(set_attr "type" "vecmove")])
@@ -5684,7 +5678,7 @@ (define_insn "lfiwax"
 ; not be needed and also in case the insns are deleted as dead code.
 
 (define_insn_and_split "floatsi<mode>2_lfiwax"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r,r")))
    (clobber (match_scratch:DI 2 "=d,wa"))]
   "TARGET_HARD_FLOAT && TARGET_LFIWAX
@@ -5723,7 +5717,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax"
    (set_attr "type" "fpload")])
 
 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(float:SFDF
 	 (sign_extend:DI
 	  (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
@@ -5747,7 +5741,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
    (set_attr "type" "fpload")])
 
 (define_insn_and_split "floatsi<SFDF:mode>2_lfiwax_<QHI:mode>_mem_zext"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(float:SFDF
 	 (zero_extend:SI
 	  (match_operand:QHI 1 "indexed_or_indirect_operand" "Z,Z"))))
@@ -5781,7 +5775,7 @@ (define_insn "lfiwzx"
    (set_attr "isa" "*,p8v,p8v,p9v")])
 
 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r,r")))
    (clobber (match_scratch:DI 2 "=d,wa"))]
   "TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
@@ -5819,7 +5813,7 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx"
    (set_attr "type" "fpload")])
 
 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unsigned_float:SFDF
 	 (zero_extend:DI
 	  (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
@@ -6019,7 +6013,7 @@ (define_expand "float<QHI:mode><FP_ISA3:mode>2"
 })
 
 (define_insn_and_split "*float<QHI:mode><FP_ISA3:mode>2_internal"
-  [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
+  [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=wa,wa,wa")
 	(float:FP_ISA3
 	 (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
    (clobber (match_scratch:DI 2 "=v,wa,v"))
@@ -6072,7 +6066,7 @@ (define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
 })
 
 (define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
-  [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
+  [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=wa,wa,wa")
 	(unsigned_float:FP_ISA3
 	 (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
    (clobber (match_scratch:DI 2 "=v,wa,wa"))
@@ -6202,7 +6196,7 @@ (define_expand "fix_trunc<mode>di2"
 
 (define_insn "*fix_trunc<mode>di2_fctidz"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
-	(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
+	(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT && TARGET_FCFID"
   "@
    fctidz %0,%1
@@ -6321,7 +6315,7 @@ (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
 
 (define_insn "fixuns_trunc<mode>di2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
-	(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
+	(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT && TARGET_FCTIDUZ"
   "@
    fctiduz %0,%1
@@ -6471,7 +6465,7 @@ (define_expand "rs6000_set_fpscr_drn"
 (define_insn "fctiwz_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
 	(unspec:DI [(fix:SI
-		     (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))]
+		     (match_operand:SFDF 1 "gpc_reg_operand" "d,wa"))]
 		   UNSPEC_FCTIWZ))]
   "TARGET_HARD_FLOAT"
   "@
@@ -6482,7 +6476,7 @@ (define_insn "fctiwz_<mode>"
 (define_insn "fctiwuz_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
 	(unspec:DI [(unsigned_fix:SI
-		     (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))]
+		     (match_operand:SFDF 1 "gpc_reg_operand" "d,wa"))]
 		   UNSPEC_FCTIWUZ))]
   "TARGET_HARD_FLOAT && TARGET_FCTIWUZ"
   "@
@@ -6585,8 +6579,8 @@ (define_insn "lrint<mode>di2"
   [(set_attr "type" "fp")])
 
 (define_insn "btrunc<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIZ))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -6595,8 +6589,8 @@ (define_insn "btrunc<mode>2"
   [(set_attr "type" "fp")])
 
 (define_insn "ceil<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIP))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -6605,8 +6599,8 @@ (define_insn "ceil<mode>2"
   [(set_attr "type" "fp")])
 
 (define_insn "floor<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIM))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -6624,8 +6618,8 @@ (define_insn "round<mode>2"
   [(set_attr "type" "fp")])
 
 (define_insn "*xsrdpi<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")]
 		     UNSPEC_XSRDPI))]
   "TARGET_HARD_FLOAT && TARGET_VSX"
   "xsrdpi %x0,%x1"
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-05-11 14:57 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-11 14:57 [PATCH 0/3] rs6000: Delete <Ff> and <Fv> Segher Boessenkool
2022-05-11 14:57 ` [PATCH 1/3] rs6000: Delete RS6000_CONSTRAINT_f Segher Boessenkool
2022-05-11 14:57 ` [PATCH 2/3] rs6000: Remove <Ff> Segher Boessenkool
2022-05-11 14:57 ` [PATCH 3/3] rs6000: Remove <Fv> Segher Boessenkool

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