From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 31D533856099 for ; Mon, 6 Jun 2022 08:44:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 31D533856099 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2568DPJ0022917; Mon, 6 Jun 2022 08:44:56 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3ggh1muh49-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 08:44:56 +0000 Received: from m0098413.ppops.net (m0098413.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2568TLQv021896; Mon, 6 Jun 2022 08:44:56 GMT Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3ggh1muh3t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 08:44:55 +0000 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 2568ZPvN021520; Mon, 6 Jun 2022 08:44:54 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma02fra.de.ibm.com with ESMTP id 3gfy191n19-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 08:44:54 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2568ipWS16646448 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 6 Jun 2022 08:44:51 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EAB37A405B; Mon, 6 Jun 2022 08:44:50 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 20514A4062; Mon, 6 Jun 2022 08:44:49 +0000 (GMT) Received: from [9.197.252.204] (unknown [9.197.252.204]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 6 Jun 2022 08:44:48 +0000 (GMT) Message-ID: <92b55526-6247-84d3-b3cc-013aeaf3b04b@linux.ibm.com> Date: Mon, 6 Jun 2022 16:44:47 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH-1, rs6000] Replace shift and ior insns with one rotate and mask insn for bswap pattern [PR93453] Content-Language: en-US To: HAO CHEN GUI Cc: Segher Boessenkool , David , Peter Bergner , gcc-patches References: From: "Kewen.Lin" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: svRKsJS3S8imW9S1ybE9WGXKxsnEqyJj X-Proofpoint-GUID: Ha3hxnxbxoZjsEHxFGWm-LXSnuf7viJD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_02,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 adultscore=0 mlxscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206060039 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, NICE_REPLY_A, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jun 2022 08:44:58 -0000 Hi Haochen, on 2022/6/6 10:21, HAO CHEN GUI wrote: > Hi, > This patch replaces shift and ior insns with one rotate and mask > insn for the split patterns which are for DI byte swap on Power6 and > before. The test cases shows the optimization. Nit: I noticed two splitting which are updated in this patch are guarded with "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" and "TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed" separately, "Power6 and before" doesn't match the later condition well. Maybe you can remove "Power6 and before" in commit log to avoid confusion. :) > > Bootstrapped and tested on ppc64 Linux BE and LE with no regressions. > Is this okay for trunk? Any recommendations? Thanks a lot. > > ChangeLog > 2022-06-06 Haochen Gui > > gcc/ > * config/rs6000/rs6000.md (split for DI load byte swap): Merge shift > and ior insns to one rotate and mask insn. > (split for DI register byte swap): Likewise. Nit: (define_split for bswapdi load) and (define_split for bswapdi reg)? > > gcc/testsuite/ > * gcc.target/powerpc/pr93453-1.c: New. > > patch.diff > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index bf85baa5370..2e38195aaac 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -2828,8 +2828,8 @@ (define_split > emit_insn (gen_bswapsi2 (dest_32, word2)); > } > > - emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32))); > - emit_insn (gen_iordi3 (dest, dest, op3)); > + emit_insn (gen_rotldi3_insert_3 (dest, op3, GEN_INT (32), dest, > + GEN_INT ((HOST_WIDE_INT_1U << 32) - 1))); Very nit: I found two other used places of gen_rotldi3_insert_3 are using GEN_INT (0xffffffff) directly, maybe it's good to keep this same with them ... > DONE; > }) > > @@ -2914,10 +2914,10 @@ (define_split > rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off); > > emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32))); > - emit_insn (gen_bswapsi2 (dest_si, src_si)); > - emit_insn (gen_bswapsi2 (op3_si, op2_si)); > - emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32))); > - emit_insn (gen_iordi3 (dest, dest, op3)); > + emit_insn (gen_bswapsi2 (op3_si, src_si)); > + emit_insn (gen_bswapsi2 (dest_si, op2_si)); > + emit_insn (gen_rotldi3_insert_3 (dest, op3, GEN_INT (32), dest, > + GEN_INT ((HOST_WIDE_INT_1U << 32) - 1))); ... Same here. OK with those nits fixed. Thanks! BR, Kewen > DONE; > }) > > diff --git a/gcc/testsuite/gcc.target/powerpc/pr93453-1.c b/gcc/testsuite/gcc.target/powerpc/pr93453-1.c > new file mode 100644 > index 00000000000..4271886561f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr93453-1.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile { target lp64 } } */ > +/* { dg-options "-mdejagnu-cpu=power6 -O2" } */ > + > +unsigned long load_byte_reverse (unsigned long *in) > +{ > + return __builtin_bswap64 (*in); > +} > + > +unsigned long byte_reverse (unsigned long in) > +{ > + return __builtin_bswap64 (in); > +} > + > +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */