[PATCH] RISC-V: Prohibit combination of 'E' and 'H'

[Tsukasa OI <research_trasio@irq.a4lg.com>]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

According to the ratified privileged specification (version 20211203),
it says:

> The hypervisor extension depends on an "I" base integer ISA with 32 x
> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.

Also in the latest draft, it also prohibits RV64E with the 'H' extension.
This commit prohibits the combination of 'E' and 'H' extensions.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
	Prohibit 'E' and 'H' combinations.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-26.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc  | 4 ++++
 gcc/testsuite/gcc.target/riscv/arch-26.c | 4 ++++
 2 files changed, 8 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-26.c

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index d7216285c648..36201559deff 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1495,6 +1495,10 @@ riscv_subset_list::parse (const char *arch, location_t loc)
     error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
 		   "extensions", arch);
 
+  /* 'H' hypervisor extension requires base ISA with 32 registers.  */
+  if (subset_list->lookup ("e") && subset_list->lookup ("h"))
+    error_at (loc, "%<-march=%s%>: h extension requires i extension", arch);
+
   return subset_list;
 
 fail:
diff --git a/gcc/testsuite/gcc.target/riscv/arch-26.c b/gcc/testsuite/gcc.target/riscv/arch-26.c
new file mode 100644
index 000000000000..0b48bc945b58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-26.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32eh -mabi=ilp32e" } */
+int foo() {}
+/* { dg-error "'-march=rv32eh': h extension requires i extension" "" { target *-*-* } 0 } */

base-commit: 66c26e5cfdf65ae024fcb658629dc5a9a10f3f85
-- 
2.42.0