diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 7cd230c4602a15980016bdc92e80579be0c07094..458a4dbf76138e329eb99077780089a9b501c046 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -27274,28 +27274,57 @@ supported_simd_type (tree t)
   return false;
 }
 
-/* Return true for types that currently are supported as SIMD return
-   or argument types.  */
+/* Determine the lane size for the clone argument/return type.  This follows
+   the LS(P) rule in the VFABIA64.  */
 
-static bool
-currently_supported_simd_type (tree t, tree b)
+static unsigned
+lane_size (cgraph_simd_clone_arg_type clone_arg_type, tree type)
 {
-  if (COMPLEX_FLOAT_TYPE_P (t))
-    return false;
+  gcc_assert (clone_arg_type != SIMD_CLONE_ARG_TYPE_MASK);
 
-  if (TYPE_SIZE (t) != TYPE_SIZE (b))
-    return false;
+  /* For non map-to-vector types that are pointers we use the element type it
+     points to.  */
+  if (POINTER_TYPE_P (type))
+    switch (clone_arg_type)
+      {
+      default:
+	break;
+      case SIMD_CLONE_ARG_TYPE_UNIFORM:
+      case SIMD_CLONE_ARG_TYPE_LINEAR_CONSTANT_STEP:
+      case SIMD_CLONE_ARG_TYPE_LINEAR_VARIABLE_STEP:
+	type = TREE_TYPE (type);
+	break;
+      }
 
-  return supported_simd_type (t);
+  /* For types (or types pointers of non map-to-vector types point to) that are
+     integers or floating point, we use their size if they are 1, 2, 4 or 8.
+   */
+  if (INTEGRAL_TYPE_P (type)
+      || SCALAR_FLOAT_TYPE_P (type))
+      switch (TYPE_PRECISION (type) / BITS_PER_UNIT)
+	{
+	default:
+	  break;
+	case 1:
+	case 2:
+	case 4:
+	case 8:
+	  return TYPE_PRECISION (type);
+	}
+  /* For any other we use the size of uintptr_t.  For map-to-vector types that
+     are pointers, using the size of uintptr_t is the same as using the size of
+     their type, seeing all pointers are the same size as uintptr_t.  */
+  return POINTER_SIZE;
 }
 
+
 /* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN.  */
 
 static int
 aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
 					struct cgraph_simd_clone *clonei,
-					tree base_type, int num,
-					bool explicit_p)
+					tree base_type ATTRIBUTE_UNUSED,
+					int num, bool explicit_p)
 {
   tree t, ret_type;
   unsigned int elt_bits, count;
@@ -27320,55 +27349,65 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
     }
 
   ret_type = TREE_TYPE (TREE_TYPE (node->decl));
+  /* According to AArch64's Vector ABI the type that determines the simdlen is
+     the narrowest of types, so we ignore base_type for AArch64.  */
   if (TREE_CODE (ret_type) != VOID_TYPE
-      && !currently_supported_simd_type (ret_type, base_type))
+      && !supported_simd_type (ret_type))
     {
       if (!explicit_p)
 	;
-      else if (TYPE_SIZE (ret_type) != TYPE_SIZE (base_type))
-	warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
-		    "GCC does not currently support mixed size types "
-		    "for %<simd%> functions");
-      else if (supported_simd_type (ret_type))
+      else if (COMPLEX_FLOAT_TYPE_P (ret_type))
 	warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
 		    "GCC does not currently support return type %qT "
-		    "for %<simd%> functions", ret_type);
+		    "for simd", ret_type);
       else
 	warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
-		    "unsupported return type %qT for %<simd%> functions",
+		    "unsupported return type %qT for simd",
 		    ret_type);
       return 0;
     }
 
+  /* We are looking for the NDS type here according to the VFABIA64, though we
+     only keep track of the ELT_BITS required to represent it.  */
+  if (TREE_CODE (ret_type) != VOID_TYPE)
+    elt_bits = lane_size (SIMD_CLONE_ARG_TYPE_VECTOR, ret_type);
+  else
+    elt_bits = 0;
+
   int i;
   tree type_arg_types = TYPE_ARG_TYPES (TREE_TYPE (node->decl));
   bool decl_arg_p = (node->definition || type_arg_types == NULL_TREE);
-
   for (t = (decl_arg_p ? DECL_ARGUMENTS (node->decl) : type_arg_types), i = 0;
        t && t != void_list_node; t = TREE_CHAIN (t), i++)
     {
       tree arg_type = decl_arg_p ? TREE_TYPE (t) : TREE_VALUE (t);
-
       if (clonei->args[i].arg_type != SIMD_CLONE_ARG_TYPE_UNIFORM
-	  && !currently_supported_simd_type (arg_type, base_type))
+	  && !supported_simd_type (arg_type))
 	{
 	  if (!explicit_p)
 	    ;
-	  else if (TYPE_SIZE (arg_type) != TYPE_SIZE (base_type))
+	  else if (COMPLEX_FLOAT_TYPE_P (ret_type))
 	    warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
-			"GCC does not currently support mixed size types "
-			"for %<simd%> functions");
+			"GCC does not currently support argument type %qT "
+			"for simd", arg_type);
 	  else
 	    warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
-			"GCC does not currently support argument type %qT "
-			"for %<simd%> functions", arg_type);
+			"unsupported argument type %qT for simd",
+			arg_type);
 	  return 0;
 	}
+      unsigned lane_bits = lane_size (clonei->args[i].arg_type, arg_type);
+      if (elt_bits > lane_bits)
+	elt_bits = lane_bits;
     }
 
+  /* If we could not determine the NDS type from available parameters/return,
+     then fallback to using uintptr_t.  */
+  if (elt_bits == 0)
+    elt_bits = POINTER_SIZE;
+
   clonei->vecsize_mangle = 'n';
   clonei->mask_mode = VOIDmode;
-  elt_bits = GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type));
   if (known_eq (clonei->simdlen, 0U))
     {
       count = 2;
@@ -27379,21 +27418,9 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
     {
       count = 1;
       vec_bits = clonei->simdlen * elt_bits;
-      /* For now, SVE simdclones won't produce illegal simdlen, So only check
-	 const simdlens here.  */
-      if (clonei->simdlen.is_constant (&const_simdlen)
-	  && maybe_ne (vec_bits, 64U) && maybe_ne (vec_bits, 128U))
-	{
-	  if (explicit_p)
-	    warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
-			"GCC does not currently support simdlen %wd for "
-			"type %qT",
-			const_simdlen, base_type);
-	  return 0;
-	}
     }
-  clonei->vecsize_int = vec_bits;
-  clonei->vecsize_float = vec_bits;
+  clonei->vecsize_int = 0;
+  clonei->vecsize_float = 0;
   return count;
 }
 
diff --git a/gcc/testsuite/c-c++-common/gomp/declare-variant-14.c b/gcc/testsuite/c-c++-common/gomp/declare-variant-14.c
index cdb0bb34f505bc9bd82a14b57d35138800bc4523..e3668893afe33a58c029cddd433d9bf43cce2bfa 100644
--- a/gcc/testsuite/c-c++-common/gomp/declare-variant-14.c
+++ b/gcc/testsuite/c-c++-common/gomp/declare-variant-14.c
@@ -15,13 +15,15 @@ int
 test1 (int x)
 {
   /* At gimplification time, we can't decide yet which function to call.  */
-  /* { dg-final { scan-tree-dump-times "f04 \\\(x" 2 "gimple" } } */
+  /* { dg-final { scan-tree-dump-times "f04 \\\(x" 2 "gimple" { target { !aarch64*-*-* } } } } */
   /* After simd clones are created, the original non-clone test1 shall
      call f03 (score 6), the sse2/avx/avx2 clones too, but avx512f clones
      shall call f01 with score 8.  */
   /* { dg-final { scan-tree-dump-not "f04 \\\(x" "optimized" } } */
-  /* { dg-final { scan-tree-dump-times "f03 \\\(x" 14 "optimized" } } */
-  /* { dg-final { scan-tree-dump-times "f01 \\\(x" 4 "optimized" } } */
+  /* { dg-final { scan-tree-dump-times "f03 \\\(x" 14 "optimized" { target { !aarch64*-*-* } } } } */
+  /* { dg-final { scan-tree-dump-times "f03 \\\(x" 10 "optimized" { target { aarch64*-*-* } } } } */
+  /* { dg-final { scan-tree-dump-times "f01 \\\(x" 4 "optimized" { target { !aarch64*-*-* } } } } */
+  /* { dg-final { scan-tree-dump-times "f01 \\\(x" 0 "optimized" { target { aarch64*-*-* } } } } */
   int a = f04 (x);
   int b = f04 (x);
   return a + b;
diff --git a/gcc/testsuite/c-c++-common/gomp/pr60823-1.c b/gcc/testsuite/c-c++-common/gomp/pr60823-1.c
index 2cc44e82c3cffa259003fa5fdbe8edd6b688d23e..5f985724daee71ae33481e84c77cf7e14d274b0a 100644
--- a/gcc/testsuite/c-c++-common/gomp/pr60823-1.c
+++ b/gcc/testsuite/c-c++-common/gomp/pr60823-1.c
@@ -17,4 +17,3 @@ foo (const double c1, const double c2)
     }
   return res;
 }
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-13 } */
diff --git a/gcc/testsuite/c-c++-common/gomp/pr60823-3.c b/gcc/testsuite/c-c++-common/gomp/pr60823-3.c
index 56ad50c41f6edeced26deaa57aea592f12c5edb1..93e9fbe3a1614e35e91629e1af79021d986b6430 100644
--- a/gcc/testsuite/c-c++-common/gomp/pr60823-3.c
+++ b/gcc/testsuite/c-c++-common/gomp/pr60823-3.c
@@ -28,6 +28,5 @@ foo (double c1, double c2)
   baz (*(struct S *)&c1, *(struct S *)&c2);
   return c1 + c2 + ((struct S *)&c1)->c[1];
 }
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-16 } */
 
 #endif
diff --git a/gcc/testsuite/g++.dg/gomp/attrs-10.C b/gcc/testsuite/g++.dg/gomp/attrs-10.C
index ed0214a8de235b3c2a6b52336106ac5de754be46..e194d88f02da23694aead60e84ab96f84c28377e 100644
--- a/gcc/testsuite/g++.dg/gomp/attrs-10.C
+++ b/gcc/testsuite/g++.dg/gomp/attrs-10.C
@@ -13,6 +13,11 @@ f1 (int l)
   return l;
 }
 
+// { dg-final { scan-assembler-times "_ZGVnN2l__Z2f1i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2l__Z2f1i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4l__Z2f1i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4l__Z2f1i:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4l__Z2f1i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4l__Z2f1i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4l__Z2f1i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -28,7 +33,7 @@ f2 (int l)
   return l + 1;
 }
 
-// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f2i:" { target { i?86-*-* x86_64-*-* } } } }
+// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f2i:" { target { i?86-*-* x86_64-*-* aarch64*-*-* } } } }
 
 int
 f3 (int l)
@@ -36,6 +41,11 @@ f3 (int l)
   return l + 2;
 }
 
+// { dg-final { scan-assembler-times "_ZGVnN2u__Z2f3i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2u__Z2f3i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4u__Z2f3i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4u__Z2f3i:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4u__Z2f3i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4u__Z2f3i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4u__Z2f3i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -51,14 +61,18 @@ f4 (int l)
   return l + 3;
 }
 
-// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f4i:" { target { i?86-*-* x86_64-*-* } } } }
+// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f4i:" { target { i?86-*-* x86_64-*-* aarch64*-*-* } } } }
 
 int
 f5 (int l)
-{	// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64*-*-* } .-1 }
+{
   return l + 4;
 }
 
+// { dg-final { scan-assembler-times "_ZGVnN4l__Z2f5i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4l__Z2f5i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN8u__Z2f5i:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4l__Z2f5i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4l__Z2f5i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4l__Z2f5i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -78,10 +92,14 @@ f5 (int l)
 int
 f6 [[omp::sequence (directive (declare simd uniform (l) simdlen (8), notinbranch),
 		    omp::directive (declare simd linear (l) simdlen (8) inbranch))]] (int l)
-{	// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64*-*-* } .-2 }
+{
   return l + 5;
 }
 
+// { dg-final { scan-assembler-times "_ZGVnN4l__Z2f6i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4u__Z2f6i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN8u__Z2f6i:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4u__Z2f6i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4l__Z2f6i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbM8l__Z2f6i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -109,7 +127,7 @@ f7 (int l)
   return l + 6;
 }
 
-// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f7i:" { target { i?86-*-* x86_64-*-* } } } }
+// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f7i:" { target { i?86-*-* x86_64-*-* aarch64*-*-* } } } }
 
 int
 f8 (int l)
@@ -117,17 +135,22 @@ f8 (int l)
   return l + 7;
 }
 
-// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f8i:" { target { i?86-*-* x86_64-*-* } } } }
+// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f8i:" { target { i?86-*-* x86_64-*-* aarch64*-*-* } } } }
 
 [[omp::sequence (omp::directive (declare variant (f7), match (construct={parallel})),
 		 directive (declare simd uniform (l), simdlen(4)))]]
 int
 f9 [[omp::directive (declare simd uniform (l) simdlen (8)),
      omp::directive (declare variant (f8) match (construct={parallel,for}))]] (int l)
-{	// { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64*-*-* } .-2 }
+{
   return l + 8;
 }
 
+// { dg-final { scan-assembler-times "_ZGVnN4u__Z2f9i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4u__Z2f9i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN8u__Z2f9i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM8u__Z2f9i:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4u__Z2f9i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4u__Z2f9i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4u__Z2f9i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -174,6 +197,9 @@ f10 (int x)
 
 template [[omp::directive (declare simd, notinbranch)]] int f10<0> (int);
 
+// { dg-final { scan-assembler-times "_ZGVnN2v__Z3f10ILi0EEii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4v__Z3f10ILi0EEii:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbN4v__Z3f10ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcN4v__Z3f10ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVdN8v__Z3f10ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -181,6 +207,9 @@ template [[omp::directive (declare simd, notinbranch)]] int f10<0> (int);
 
 template  int f10<1> [[omp::directive (declare simd inbranch linear(x))]] (int x);
 
+// { dg-final { scan-assembler-times "_ZGVnM2l__Z3f10ILi1EEii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4l__Z3f10ILi1EEii:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4l__Z3f10ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4l__Z3f10ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVdM8l__Z3f10ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -195,6 +224,9 @@ f11<0> (int x)
   return x;
 }
 
+// { dg-final { scan-assembler-times "_ZGVnM2v__Z3f11ILi0EEii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4v__Z3f11ILi0EEii:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4v__Z3f11ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4v__Z3f11ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVdM8v__Z3f11ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -206,6 +238,9 @@ f11<1> [[omp::directive (declare simd, notinbranch, linear (y))]] (int y)
   return y;
 }
 
+// { dg-final { scan-assembler-times "_ZGVnN2l__Z3f11ILi1EEii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4l__Z3f11ILi1EEii:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbN4l__Z3f11ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcN4l__Z3f11ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVdN8l__Z3f11ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -223,6 +258,9 @@ S::f12 (int x)
   return x;
 }
 
+// { dg-final { scan-assembler-times "_ZGVnM2uv__ZN1S3f12Ei:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2uv__ZN1S3f12Ei:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4uv__ZN1S3f12Ei:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4uv__ZN1S3f12Ei:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVdM8uv__ZN1S3f12Ei:" 1 { target { i?86-*-* x86_64-*-* } } } }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C
index 00996b60e52760bf9fe82de7b0c42b9c846c1272..61a3b31704dd997f65268e91b4cbf1b9b07e67fd 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C
@@ -14,7 +14,9 @@ int f2 (int a, int *b, int c)
   return a + *b + c;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN8uva32l4__Z2f2iPii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM8uva32l4__Z2f2iPii:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -82,6 +84,9 @@ namespace N1
   }
 }
 
+// { dg-final { scan-assembler-times "_ZGVnN2va16__ZN2N12N23f10EPx:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2va16__ZN2N12N23f10EPx:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -193,8 +198,9 @@ int B<int>::f25<7> (int a, int *b, int c)
 {
   return a + *b + c;
 }
+// { dg-final { scan-assembler-times "_ZGVnN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { aarch64*-*-* } } } }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
 // { dg-final { scan-assembler-times "_ZGVbM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -212,7 +218,9 @@ int B<int>::f26<-1> (int a, int *b, int c)
   return a + *b + c;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -244,7 +252,9 @@ f30 (int x)
   return x;
 }
 
-// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64*-*-* } .-7 }
+// { dg-final { scan-assembler-times "_ZGVnN16v__Z3f30i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM16v__Z3f30i:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -287,7 +297,6 @@ struct D
   int f37 (int a);
   int e;
 };
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-3 }
 
 void
 f38 (D &d)
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C
index ee4ab6febd0dfc727e57fce9438b2e9001075155..d89d9a7cf6b5aca4d69d819abbd975a7773ab824 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C
@@ -13,7 +13,11 @@ int f1 (int a, int b, int c, int &d, int &e, int &f)
   return a + b + c + d + e + f;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-11 }
+// { dg-final { scan-assembler-times "_ZGVnN2vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -42,7 +46,11 @@ int f2 (int a, int b, int c, int &d, int &e, int &f)
   return a + b + c + d + e + f;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-17 }
+// { dg-final { scan-assembler-times "_ZGVnN2vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -58,7 +66,11 @@ int f3 (const int a, const int b, const int c, const int &d, const int &e, const
   return a + b + c + d + e + f;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN2vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -80,7 +92,11 @@ int f4 (const int a, const int b, const int c, const int &d, const int &e, const
   return a + b + c + d + e + f;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-11 }
+// { dg-final { scan-assembler-times "_ZGVnN2vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C
index d76defbc93319e94e23086250defc65758af18fc..a671108cd9dafd9be806bdc281e017c712458ece 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C
@@ -5,7 +5,11 @@ f1 (int *p, int *q, short *s)
   return *p + *q + *s;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVbN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -22,7 +26,8 @@ f2 (int *p, short *q, int s, int r, int &t)
   return *p + *q + r;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -35,7 +40,8 @@ f3 (int &p, short &q, int s, int &r, int &t)
   return p + q + r;
 }
 
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { aarch64*-*-* } } } }
+
 // { dg-final { scan-assembler-times "_ZGVbN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVcN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
 // { dg-final { scan-assembler-times "_ZGVdN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-7.C b/gcc/testsuite/g++.dg/gomp/declare-simd-7.C
index 373be28ebd325b254b1f467c2ad761479e26685b..52e9f182da35c920d78e64da8ee56cfdabaea541 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-7.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-7.C
@@ -18,7 +18,6 @@ foo1 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
 {
   return bar1 (a, b, c, d, e, f, g, h, i, j, k);
 }
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
 
 #pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \
 		    linear (f : 2) linear (ref (g) : 1) \
@@ -29,7 +28,6 @@ foo2 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
 {
   return bar2 (a, b, c, d, e, f, g, h, i, j, k);
 }
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
 
 #pragma omp declare simd notinbranch uniform (b, c, d, e) aligned (e : 16) \
 		    linear (f : 2) linear (ref (g) : 1) \
@@ -40,7 +38,6 @@ foo3 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
 {
   return bar3 (a, b, c, d, e, f, g, h, i, j, k);
 }
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
 
 #pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \
 		    linear (f : 2) linear (ref (g) : 1) \
@@ -51,4 +48,3 @@ foo4 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
 {
   return bar4 (a, b, c, d, e, f, g, h, i, j, k);
 }
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-8.C b/gcc/testsuite/g++.dg/gomp/declare-simd-8.C
index ef183136833a997e2009af367acb575e02cb5b22..01c91e890914315ccd50e11cbeb5ff7581491a7d 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-8.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-8.C
@@ -4,7 +4,6 @@ template <int N, typename T>
 struct S {
   #pragma omp declare simd aligned(a : N * 2) aligned(b) linear(ref(b): N)
   float foo (float *a, T *&b) { return *a + *b; }
-  // { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-1 }
 };
 
 S<16, float> s;
diff --git a/gcc/testsuite/g++.dg/gomp/pr88182.C b/gcc/testsuite/g++.dg/gomp/pr88182.C
index 504f50376408543d4bbce55dbcc8f0f06b0fd805..6eeeed9fff7792daa053622e37c8548650ce87d3 100644
--- a/gcc/testsuite/g++.dg/gomp/pr88182.C
+++ b/gcc/testsuite/g++.dg/gomp/pr88182.C
@@ -18,7 +18,6 @@ foo (double c1, double c2)
     }
   return res;
 }
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-15 }
 
 __attribute__((noinline, noclone)) void
 bar (double *x, double *y)
diff --git a/gcc/testsuite/gcc.dg/declare-simd.c b/gcc/testsuite/gcc.dg/declare-simd.c
index 2c8c1b7da4f3249c714849fa226bfa2fe64a2b88..1c71b60c97427705e2751088e24840e2613b4f03 100644
--- a/gcc/testsuite/gcc.dg/declare-simd.c
+++ b/gcc/testsuite/gcc.dg/declare-simd.c
@@ -3,7 +3,6 @@
 
 #pragma omp declare simd linear (p2, p3)
 extern void fn2 (float p1, float *p2, float *p3);
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target { { aarch64*-*-* } && lp64 } } .-1 } */
 
 float *a, *b;
 void fn1 (float *p1)
diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c
index add322873e64590ff3187f20907687ef34991fcb..b8bba1f892b6d1fb6885a47f4b7ef78f7caba7ef 100644
--- a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c
+++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c
@@ -13,7 +13,6 @@ int f2 (int a, int *b, int c)
   return a + *b + c;
 }
 
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
 /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -50,7 +49,6 @@ f7 (int x)
   return x;
 }
 
-/* { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64*-*-* } .-7 } */
 /* { dg-final { scan-assembler-times "_ZGVbM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -70,7 +68,6 @@ f13 (int c; int *b; int a; int a, int *b, int c)
   return a + *b + c;
 }
 
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
 /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -89,7 +86,6 @@ f14 (a, b, c)
   return a + *b + c;
 }
 
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-7 } */
 /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -106,7 +102,6 @@ f15 (int a, int *b, int c)
   return a + *b + c;
 }
 
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
 /* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -128,7 +123,6 @@ int f17 (int g, long *h)
   return g + h[0];
 }
 
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
 /* { dg-final { scan-assembler-times "_ZGVbM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
@@ -155,7 +149,6 @@ f18 (j, i)
   return j + i[0];
 }
 
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-7 } */
 /* { dg-final { scan-assembler-times "_ZGVbM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c
index bf01c023541ae2100f63887901f4f330fbf1a12f..71241d2569a149d828e9702d71fba65d7497d0c2 100644
--- a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c
+++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c
@@ -4,8 +4,10 @@ f1 (int *p, int *q, short *s)
 {
   return *p + *q + *s;
 }
-
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
+/* { dg-final { scan-assembler-times "_ZGVnM4l4ln4ln6_f1:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN4l4ln4ln6_f1:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnM8l4ln4ln6_f1:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN8l4ln4ln6_f1:" 1 { target { aarch64*-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbM4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcM4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -22,7 +24,7 @@ f2 (int *p, short *q, int s, int r, int t)
   return *p + *q + r;
 }
 
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
+/* { dg-final { scan-assembler-times "_ZGVnN8ls2ls4uls2u_f2:" 1 { target { aarch64*-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
 /* { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
diff --git a/gcc/testsuite/gcc.dg/gomp/pr87887-1.c b/gcc/testsuite/gcc.dg/gomp/pr87887-1.c
index 8b04ffd0809be4e6f5ab97c2e32e800edffbee4f..6e143aa0b5aa5ff9a9e13298fd44059377bc4f2e 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr87887-1.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr87887-1.c
@@ -10,6 +10,7 @@ foo (int x)
 {
   return (struct S) { x };
 }
+/* { dg-warning "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 } */
 
 #pragma omp declare simd
 int
@@ -17,6 +18,7 @@ bar (struct S x)
 {
   return x.n;
 }
+/* { dg-warning "unsupported argument type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 } */
 
 #pragma omp declare simd uniform (x)
 int
diff --git a/gcc/testsuite/gcc.dg/gomp/pr87895-1.c b/gcc/testsuite/gcc.dg/gomp/pr87895-1.c
index 7338f18d192072c4447957f3f20a32545c961d7f..22f5c691416470d6e0b9b02c97e519356bd39123 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr87895-1.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr87895-1.c
@@ -17,4 +17,3 @@ bar (int *x, int y)
   if ((y == 0) ? (*x = 0) : *x)
     return 0;
 }
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
diff --git a/gcc/testsuite/gcc.dg/gomp/pr89246-1.c b/gcc/testsuite/gcc.dg/gomp/pr89246-1.c
index dfe629c1c6a51624cd94878c638606220cfe94eb..cdaec6b385169fc5ebb71dca48ef10c64c2cecfa 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr89246-1.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr89246-1.c
@@ -8,6 +8,7 @@ int foo (__int128 x)
 {
   return x;
 }
+/* { dg-warning "unsupported argument type ‘__int128’ for ‘simd’ functions" { target aarch64*-*-* } .-4 } */
 
 #pragma omp declare simd
 extern int bar (int x);
diff --git a/gcc/testsuite/gcc.dg/gomp/pr99542.c b/gcc/testsuite/gcc.dg/gomp/pr99542.c
index b67ff5a37a20fdc2791b0aa9254a18d5ac43247e..f38e21da18580798bd2789c437cb0747da317efb 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr99542.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr99542.c
@@ -3,8 +3,8 @@
 /* { dg-options "-O0 -fopenmp-simd" } */
 
 #pragma omp declare simd
-extern int foo (__int128 x);	/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } } */
-/* { dg-warning "unsupported argument type '__int128' for simd" "" { target i?86-*-* x86_64-*-* } .-1 } */
+extern int foo (__int128 x);
+/* { dg-warning "unsupported argument type '__int128' for simd" "" { target i?86-*-* x86_64-*-* aarch64*-*-* } .-1 } */
 
 #pragma omp declare simd uniform (x)
 extern int baz (__int128 x);
diff --git a/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c b/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c
index 9f7c84dc70ba4770c5f63f8af863e5577608d9a8..5fe4069c01c199a78c5f076f5a8ed1031da51cec 100644
--- a/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c
+++ b/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c
@@ -6,7 +6,6 @@ int addit(int a, int b, int *c)
 {
   return a + b;
 }
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 } */
 /* { dg-final { scan-tree-dump {(?n)^__attribute__\(\(omp declare simd \(notinbranch aligned\(2:32\)\), omp declare simd \(inbranch uniform\(2\) linear\(1:66\)\)\)\)$} "optimized" } } */
 
 #pragma omp declare simd uniform(a) aligned(a:32) linear(k:1) notinbranch
@@ -17,6 +16,13 @@ float setArray(float *a, float x, int k)
 }
 /* { dg-final { scan-tree-dump {(?n)^__attribute__\(\(omp declare simd \(notinbranch uniform\(0\) aligned\(0:32\) linear\(2:1\)\)\)\)$} "optimized" } } */
 
+/* { dg-final { scan-tree-dump "_ZGVnN2ua32vl_setArray" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnN4ua32vl_setArray" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnN2vvva32_addit" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnN4vvva32_addit" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnM2vl66u_addit" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnM4vl66u_addit" "optimized { target aarch64*-*-* } } } */
+
 /* { dg-final { scan-tree-dump "_ZGVbN4ua32vl_setArray" "optimized" { target i?86-*-* x86_64-*-* } } } */
 /* { dg-final { scan-tree-dump "_ZGVbN4vvva32_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */
 /* { dg-final { scan-tree-dump "_ZGVbM4vl66u_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */
diff --git a/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90 b/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90
index bbf70d9664a74601bed1d3352c0c33145e8fc8e7..8f76774fd6e0cc3a4ee327161496524392833179 100644
--- a/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90
@@ -1,6 +1,6 @@
 ! { dg-do compile }
 
-function f1 (a, b, c, d, e, f) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+function f1 (a, b, c, d, e, f)
   integer, value :: a, b, c
   integer :: d, e, f, f1
 !$omp declare simd (f1) uniform(b) linear(c, d) linear(uval(e)) linear(ref(f))
@@ -12,7 +12,7 @@ function f1 (a, b, c, d, e, f) ! { dg-warning "GCC does not currently support mi
   f = f + 1
   f1 = a + b + c + d + e + f
 end function f1
-integer function f2 (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+integer function f2 (a, b)
   integer :: a, b
 !$omp declare simd uniform(b) linear(ref(a):b)
   a = a + 1
diff --git a/gcc/testsuite/gfortran.dg/gomp/declare-simd-coarray-lib.f90 b/gcc/testsuite/gfortran.dg/gomp/declare-simd-coarray-lib.f90
index f0c4e39efba140550f25c1b283d8eca66760f3a9..1f74da76ffe3f45b85e7f89534b7bf2ab923b4ff 100644
--- a/gcc/testsuite/gfortran.dg/gomp/declare-simd-coarray-lib.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/declare-simd-coarray-lib.f90
@@ -5,7 +5,7 @@
 ! Failed as TREE_TYPE(fndecl) did not include the
 ! hidden caf_token/caf_offset arguments.
 !
-integer function f(x)	! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+integer function f(x)
    integer :: x[*]
    !$omp declare simd
    f = x[1]
diff --git a/gcc/testsuite/gfortran.dg/gomp/declare-variant-14.f90 b/gcc/testsuite/gfortran.dg/gomp/declare-variant-14.f90
index 06c9a5d1ed8f9a5c0bbb4201e505f4309ef56222..66ffcf2e3feb1bd3e5bb43c9b7731ffd7a2aad22 100644
--- a/gcc/testsuite/gfortran.dg/gomp/declare-variant-14.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/declare-variant-14.f90
@@ -35,13 +35,15 @@ contains
     integer :: a, b
 
     ! At gimplification time, we can't decide yet which function to call.
-    ! { dg-final { scan-tree-dump-times "f04 \\\(x" 2 "gimple" } }
+    ! { dg-final { scan-tree-dump-times "f04 \\\(x" 2 "gimple" { target { !aarch64*-*-* } } } }
     ! After simd clones are created, the original non-clone test1 shall
     ! call f03 (score 6), the sse2/avx/avx2 clones too, but avx512f clones
     ! shall call f01 with score 8.
     ! { dg-final { scan-tree-dump-not "f04 \\\(x" "optimized" } }
-    ! { dg-final { scan-tree-dump-times "f03 \\\(x" 14 "optimized" } }
-    ! { dg-final { scan-tree-dump-times "f01 \\\(x" 4 "optimized" } }
+    ! { dg-final { scan-tree-dump-times "f03 \\\(x" 14 "optimized" { target { !aarch64*-*-* } } } }
+    ! { dg-final { scan-tree-dump-times "f03 \\\(x" 10 "optimized" { target { aarch64*-*-* } } } }
+    ! { dg-final { scan-tree-dump-times "f01 \\\(x" 4 "optimized" { target { !aarch64*-*-* } } } }
+    ! { dg-final { scan-tree-dump-times "f01 \\\(x" 0 "optimized" { target { aarch64*-*-* } } } }
     a = f04 (x)
     b = f04 (x)
     test1 = a + b
diff --git a/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90 b/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90
index ea147bfa78ec716b7534f9b098c1fc0b98b1d397..6376baa6383c5527a6f9b8138d2b801f0fa53d5d 100644
--- a/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90
@@ -1,7 +1,7 @@
 ! PR fortran/79154
 ! { dg-do compile }
 
-pure real function foo (a, b)		! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+pure real function foo (a, b)
 !$omp declare simd(foo)			! { dg-bogus "may not appear in PURE" }
   real, intent(in) :: a, b
   foo = a + b
@@ -20,7 +20,7 @@ pure real function baz (a, b)
   real, intent(in) :: a, b
   baz = a + b
 end function baz
-elemental real function fooe (a, b)	! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+elemental real function fooe (a, b)
 !$omp declare simd(fooe)		! { dg-bogus "may not appear in PURE" }
   real, intent(in) :: a, b
   fooe = a + b
diff --git a/gcc/testsuite/gfortran.dg/gomp/pr83977.f90 b/gcc/testsuite/gfortran.dg/gomp/pr83977.f90
index ea8e229fe5486a645cc7cc8aae748725f979c448..b8ad1a7e39c184fd084658477b183fc93071b357 100644
--- a/gcc/testsuite/gfortran.dg/gomp/pr83977.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/pr83977.f90
@@ -1,7 +1,7 @@
 ! PR middle-end/83977
 ! { dg-do compile }
 
-integer function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+integer function foo (a, b)
    integer :: a, b
 !$omp declare simd uniform(b) linear(ref(a):b)
    a = a + 1
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 7004711b3848d4ceb2319526928156b82f525d32..e85852f15357b1a6202c5592381d96d43565974c 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4028,7 +4028,8 @@ proc check_effective_target_vect_simd_clones { } {
     return [check_cached_effective_target_indexed vect_simd_clones {
       expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
 	      && [check_effective_target_avx512f])
-	     || [istarget amdgcn-*-*] }}]
+	     || [istarget amdgcn-*-*]
+	     || [istarget aarch64*-*-*] }}]
 }
 
 # Return 1 if this is a AArch64 target supporting big endian