From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by sourceware.org (Postfix) with ESMTPS id 3F6BE3858D28; Mon, 6 Dec 2021 16:32:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3F6BE3858D28 Received: by mail-wr1-x432.google.com with SMTP id a9so23588828wrr.8; Mon, 06 Dec 2021 08:32:23 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:mime-version:subject:message-id:date:cc:to; bh=+qtsytkPdxn/WghgODndlr3oxYTPNm0mAapWHzsPTv8=; b=nDGFmeGG146GoporGsSow4LzJNB3mOuFJftQOTsJwC4nFcAUmfnTyifeaC8uJW5vAS VRZe3wgksyriv9n1gsH9ZP27Uw4X+t6s6myEl2ZQyMHCO+V3f52oawYDPUGpOL3Dn7cL l/wvSZmWLK+Cip8yIfA48vmj5WYEQcK4zncZAa+NMBdPivZ5DNRhM93hS9QBjgOzAMrp h6/wF2JEt1GlRlgTooGiHUWyPXFhNInlY2z9wfd7hb0hl9OvDgenjVvPEGCJnWuqnqEZ 8I8qL39pHZB+6TkIe63XaYZfF7heY0NRSwhahut8Ojtb2nULicGnRIJNvJs7kjPTCABi IXBw== X-Gm-Message-State: AOAM53283GTynv7dNxtl9a0N8W+QOWEVpt05AXrJCnHwSQNKell/SNRT FNjqjy3pA4xIbnV4Gm+k6upvYnAQkOU= X-Google-Smtp-Source: ABdhPJxRM5arkVKq0ORVqPyQZba9xhDujBVU1PbmJzqaOgaxhk2aTzu8+1PidjxTAS/pzOtgUoNnZg== X-Received: by 2002:a5d:6dc1:: with SMTP id d1mr43771811wrz.282.1638808342237; Mon, 06 Dec 2021 08:32:22 -0800 (PST) Received: from smtpclient.apple (chp127.enscp.fr. [193.51.253.127]) by smtp.gmail.com with ESMTPSA id y6sm13801016wma.37.2021.12.06.08.32.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Dec 2021 08:32:20 -0800 (PST) From: FX Content-Type: multipart/mixed; boundary="Apple-Mail=_60519DB6-00A5-4714-827F-4A8013DB149F" Mime-Version: 1.0 (Mac OS X Mail 15.0 \(3693.20.0.1.32\)) Subject: [patch, Fortran] IEEE support for aarch64-apple-darwin Message-Id: <93D8CCF9-4230-4517-A993-A811092ADC4B@gmail.com> Date: Mon, 6 Dec 2021 17:32:19 +0100 Cc: gcc-patches@gcc.gnu.org To: fortran@gcc.gnu.org X-Mailer: Apple Mail (2.3693.20.0.1.32) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Dec 2021 16:32:24 -0000 --Apple-Mail=_60519DB6-00A5-4714-827F-4A8013DB149F Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 Hi everyone, Since support for target aarch64-apple-darwin has been submitted for = review, it=E2=80=99s time to submit the Fortran part, i.e. enabling IEEE = support on that target. The patch has been in use now for several months, in a developer branch = shipped by some distros on macOS (including Homebrew). It was authored = more than a year ago, but I figured it wasn=E2=80=99t relevant to submit = until the target was actually close to be in trunk: = https://github.com/iains/gcc-darwin-arm64/commit/b107973550d3d9a9ce9acc751= adbbe2171d13736 Bootstrapped and tested on aarch64-apple-darwin20 (macOS Big Sur) and = aarch64-apple-darwin21 (macOS Monterey). OK to merge? Can someone point me to the right way of formatting ChangeLogs and = commit entries, nowadays? Thanks, FX --Apple-Mail=_60519DB6-00A5-4714-827F-4A8013DB149F Content-Disposition: attachment; filename=b107973550d3d9a9ce9acc751adbbe2171d13736.patch Content-Type: application/octet-stream; x-unix-mode=0644; name="b107973550d3d9a9ce9acc751adbbe2171d13736.patch" Content-Transfer-Encoding: quoted-printable =46rom=20b107973550d3d9a9ce9acc751adbbe2171d13736=20Mon=20Sep=2017=20= 00:00:00=202001=0AFrom:=20FX=20Coudert=20=0ADate:=20= Tue,=201=20Sep=202020=2017:41:43=20+0200=0ASubject:=20[PATCH]=20Add=20= IEEE=20code=20for=20Aarch64=20in=20libgfortran=0A=0A---=0A=20= libgfortran/config/fpu-aarch64.h=20|=20322=20= +++++++++++++++++++++++++++++++=0A=20libgfortran/configure.host=20=20=20=20= =20=20=20|=20=2018=20+-=0A=202=20files=20changed,=20337=20insertions(+),=20= 3=20deletions(-)=0A=20create=20mode=20100644=20= libgfortran/config/fpu-aarch64.h=0A=0Adiff=20--git=20= a/libgfortran/config/fpu-aarch64.h=20b/libgfortran/config/fpu-aarch64.h=0A= new=20file=20mode=20100644=0Aindex=20000000000000..4db1b6c4f6b6=0A---=20= /dev/null=0A+++=20b/libgfortran/config/fpu-aarch64.h=0A@@=20-0,0=20= +1,322=20@@=0A+/*=20FPU-related=20code=20for=20aarch64.=0A+=20=20=20= Copyright=20(C)=202020=20Free=20Software=20Foundation,=20Inc.=0A+=20=20=20= Contributed=20by=20Francois-Xavier=20Coudert=20=0A= +=0A+This=20file=20is=20part=20of=20the=20GNU=20Fortran=20runtime=20= library=20(libgfortran).=0A+=0A+Libgfortran=20is=20free=20software;=20= you=20can=20redistribute=20it=20and/or=0A+modify=20it=20under=20the=20= terms=20of=20the=20GNU=20General=20Public=0A+License=20as=20published=20= by=20the=20Free=20Software=20Foundation;=20either=0A+version=203=20of=20= the=20License,=20or=20(at=20your=20option)=20any=20later=20version.=0A+=0A= +Libgfortran=20is=20distributed=20in=20the=20hope=20that=20it=20will=20= be=20useful,=0A+but=20WITHOUT=20ANY=20WARRANTY;=20without=20even=20the=20= implied=20warranty=20of=0A+MERCHANTABILITY=20or=20FITNESS=20FOR=20A=20= PARTICULAR=20PURPOSE.=20=20See=20the=0A+GNU=20General=20Public=20License=20= for=20more=20details.=0A+=0A+Under=20Section=207=20of=20GPL=20version=20= 3,=20you=20are=20granted=20additional=0A+permissions=20described=20in=20= the=20GCC=20Runtime=20Library=20Exception,=20version=0A+3.1,=20as=20= published=20by=20the=20Free=20Software=20Foundation.=0A+=0A+You=20should=20= have=20received=20a=20copy=20of=20the=20GNU=20General=20Public=20License=20= and=0A+a=20copy=20of=20the=20GCC=20Runtime=20Library=20Exception=20along=20= with=20this=20program;=0A+see=20the=20files=20COPYING3=20and=20= COPYING.RUNTIME=20respectively.=20=20If=20not,=20see=0A= +.=20=20*/=0A+=0A+=0A+/*=20Rounding=20mask=20= and=20modes=20*/=0A+=0A+#define=20FPCR_RM_MASK=20=200xc00000=0A+#define=20= FE_TONEAREST=20=200x000000=0A+#define=20FE_UPWARD=20=20=20=20=200x400000=0A= +#define=20FE_DOWNWARD=20=20=200x800000=0A+#define=20FE_TOWARDZERO=20= 0xc00000=0A+=0A+/*=20Exceptions=20*/=0A+=0A+#define=20FE_INVALID=091=0A= +#define=20FE_DIVBYZERO=092=0A+#define=20FE_OVERFLOW=094=0A+#define=20= FE_UNDERFLOW=098=0A+#define=20FE_INEXACT=0916=0A+=0A+#define=20= FE_ALL_EXCEPT=20(FE_INVALID=20|=20FE_DIVBYZERO=20|=20FE_OVERFLOW=20|=20= FE_UNDERFLOW=20|=20FE_INEXACT)=0A+#define=20FE_EXCEPT_SHIFT=098=0A+=0A+=0A= +=0A+/*=20This=20structure=20corresponds=20to=20the=20layout=20of=20the=20= block=0A+=20=20=20written=20by=20FSTENV.=20=20*/=0A+struct=20fenv=0A+{=0A= +=20=20unsigned=20int=20__fpcr;=0A+=20=20unsigned=20int=20__fpsr;=0A+};=0A= +=0A+/*=20Check=20we=20can=20actually=20store=20the=20FPU=20state=20in=20= the=20allocated=20size.=20=20*/=0A+_Static_assert=20(sizeof(struct=20= fenv)=20<=3D=20(size_t)=20GFC_FPE_STATE_BUFFER_SIZE,=0A+=09=09= "GFC_FPE_STATE_BUFFER_SIZE=20is=20too=20small");=0A+=0A+=0A+=0A+void=0A= +set_fpu=20(void)=0A+{=0A+=20=20if=20(options.fpe=20&=20= GFC_FPE_DENORMAL)=0A+=20=20=20=20estr_write=20("Fortran=20runtime=20= warning:=20Floating=20point=20'denormal=20operand'=20"=0A+=09=20=20=20=20= =20=20=20=20"exception=20not=20supported.\n");=0A+=0A+=20=20= set_fpu_trap_exceptions=20(options.fpe,=200);=0A+}=0A+=0A+=0A+int=0A= +get_fpu_trap_exceptions=20(void)=0A+{=0A+=20=20unsigned=20int=20fpcr,=20= exceptions;=0A+=20=20int=20res=20=3D=200;=0A+=0A+=20=20fpcr=20=3D=20= __builtin_aarch64_get_fpcr();=0A+=20=20exceptions=20=3D=20(fpcr=20>>=20= FE_EXCEPT_SHIFT)=20&=20FE_ALL_EXCEPT;=0A+=0A+=20=20if=20(exceptions=20&=20= FE_INVALID)=20res=20|=3D=20GFC_FPE_INVALID;=0A+=20=20if=20(exceptions=20= &=20FE_DIVBYZERO)=20res=20|=3D=20GFC_FPE_ZERO;=0A+=20=20if=20(exceptions=20= &=20FE_OVERFLOW)=20res=20|=3D=20GFC_FPE_OVERFLOW;=0A+=20=20if=20= (exceptions=20&=20FE_UNDERFLOW)=20res=20|=3D=20GFC_FPE_UNDERFLOW;=0A+=20=20= if=20(exceptions=20&=20FE_INEXACT)=20res=20|=3D=20GFC_FPE_INEXACT;=0A+=0A= +=20=20return=20res;=0A+}=0A+=0A+=0A+void=20set_fpu_trap_exceptions=20= (int=20trap,=20int=20notrap)=0A+{=0A+=20=20unsigned=20int=20mode_set=20=3D= =200,=20mode_clr=20=3D=200;=0A+=20=20unsigned=20int=20fpsr,=20fpsr_new;=0A= +=20=20unsigned=20int=20fpcr,=20fpcr_new;=0A+=0A+=20=20if=20(trap=20&=20= GFC_FPE_INVALID)=0A+=20=20=20=20mode_set=20|=3D=20FE_INVALID;=0A+=20=20= if=20(notrap=20&=20GFC_FPE_INVALID)=0A+=20=20=20=20mode_clr=20|=3D=20= FE_INVALID;=0A+=0A+=20=20if=20(trap=20&=20GFC_FPE_ZERO)=0A+=20=20=20=20= mode_set=20|=3D=20FE_DIVBYZERO;=0A+=20=20if=20(notrap=20&=20= GFC_FPE_ZERO)=0A+=20=20=20=20mode_clr=20|=3D=20FE_DIVBYZERO;=0A+=0A+=20=20= if=20(trap=20&=20GFC_FPE_OVERFLOW)=0A+=20=20=20=20mode_set=20|=3D=20= FE_OVERFLOW;=0A+=20=20if=20(notrap=20&=20GFC_FPE_OVERFLOW)=0A+=20=20=20=20= mode_clr=20|=3D=20FE_OVERFLOW;=0A+=0A+=20=20if=20(trap=20&=20= GFC_FPE_UNDERFLOW)=0A+=20=20=20=20mode_set=20|=3D=20FE_UNDERFLOW;=0A+=20=20= if=20(notrap=20&=20GFC_FPE_UNDERFLOW)=0A+=20=20=20=20mode_clr=20|=3D=20= FE_UNDERFLOW;=0A+=0A+=20=20if=20(trap=20&=20GFC_FPE_INEXACT)=0A+=20=20=20= =20mode_set=20|=3D=20FE_INEXACT;=0A+=20=20if=20(notrap=20&=20= GFC_FPE_INEXACT)=0A+=20=20=20=20mode_clr=20|=3D=20FE_INEXACT;=0A+=0A+=20=20= /*=20Clear=20stalled=20exception=20flags.=20=20*/=0A+=20=20fpsr=20=3D=20= __builtin_aarch64_get_fpsr();=0A+=20=20fpsr_new=20=3D=20fpsr=20&=20= ~FE_ALL_EXCEPT;=0A+=20=20if=20(fpsr_new=20!=3D=20fpsr)=0A+=20=20=20=20= __builtin_aarch64_set_fpsr(fpsr_new);=0A+=0A+=20=20fpcr_new=20=3D=20fpcr=20= =3D=20__builtin_aarch64_get_fpcr();=0A+=20=20fpcr_new=20|=3D=20(mode_set=20= <<=20FE_EXCEPT_SHIFT);=0A+=20=20fpcr_new=20&=3D=20~(mode_clr=20<<=20= FE_EXCEPT_SHIFT);=0A+=0A+=20=20if=20(fpcr_new=20!=3D=20fpcr)=0A+=20=20=20= =20__builtin_aarch64_set_fpcr(fpcr_new);=0A+}=0A+=0A+=0A+int=0A= +support_fpu_flag=20(int=20flag)=0A+{=0A+=20=20if=20(flag=20&=20= GFC_FPE_DENORMAL)=0A+=20=20=20=20return=200;=0A+=0A+=20=20return=201;=0A= +}=0A+=0A+=0A+int=0A+support_fpu_trap=20(int=20flag)=0A+{=0A+=20=20if=20= (flag=20&=20GFC_FPE_DENORMAL)=0A+=20=20=20=20return=200;=0A+=0A+=20=20= return=201;=0A+}=0A+=0A+=0A+int=0A+get_fpu_except_flags=20(void)=0A+{=0A= +=20=20int=20result;=0A+=20=20unsigned=20int=20fpsr;=0A+=0A+=20=20result=20= =3D=200;=0A+=20=20fpsr=20=3D=20__builtin_aarch64_get_fpsr()=20&=20= FE_ALL_EXCEPT;=0A+=0A+=20=20if=20(fpsr=20&=20FE_INVALID)=0A+=20=20=20=20= result=20|=3D=20GFC_FPE_INVALID;=0A+=20=20if=20(fpsr=20&=20FE_DIVBYZERO)=0A= +=20=20=20=20result=20|=3D=20GFC_FPE_ZERO;=0A+=20=20if=20(fpsr=20&=20= FE_OVERFLOW)=0A+=20=20=20=20result=20|=3D=20GFC_FPE_OVERFLOW;=0A+=20=20= if=20(fpsr=20&=20FE_UNDERFLOW)=0A+=20=20=20=20result=20|=3D=20= GFC_FPE_UNDERFLOW;=0A+=20=20if=20(fpsr=20&=20FE_INEXACT)=0A+=20=20=20=20= result=20|=3D=20GFC_FPE_INEXACT;=0A+=0A+=20=20return=20result;=0A+}=0A+=0A= +=0A+void=0A+set_fpu_except_flags=20(int=20set,=20int=20clear)=0A+{=0A+=20= =20unsigned=20int=20exc_set=20=3D=200,=20exc_clr=20=3D=200;=0A+=20=20= unsigned=20int=20fpsr,=20fpsr_new;=0A+=0A+=20=20if=20(set=20&=20= GFC_FPE_INVALID)=0A+=20=20=20=20exc_set=20|=3D=20FE_INVALID;=0A+=20=20= else=20if=20(clear=20&=20GFC_FPE_INVALID)=0A+=20=20=20=20exc_clr=20|=3D=20= FE_INVALID;=0A+=0A+=20=20if=20(set=20&=20GFC_FPE_ZERO)=0A+=20=20=20=20= exc_set=20|=3D=20FE_DIVBYZERO;=0A+=20=20else=20if=20(clear=20&=20= GFC_FPE_ZERO)=0A+=20=20=20=20exc_clr=20|=3D=20FE_DIVBYZERO;=0A+=0A+=20=20= if=20(set=20&=20GFC_FPE_OVERFLOW)=0A+=20=20=20=20exc_set=20|=3D=20= FE_OVERFLOW;=0A+=20=20else=20if=20(clear=20&=20GFC_FPE_OVERFLOW)=0A+=20=20= =20=20exc_clr=20|=3D=20FE_OVERFLOW;=0A+=0A+=20=20if=20(set=20&=20= GFC_FPE_UNDERFLOW)=0A+=20=20=20=20exc_set=20|=3D=20FE_UNDERFLOW;=0A+=20=20= else=20if=20(clear=20&=20GFC_FPE_UNDERFLOW)=0A+=20=20=20=20exc_clr=20|=3D=20= FE_UNDERFLOW;=0A+=0A+=20=20if=20(set=20&=20GFC_FPE_INEXACT)=0A+=20=20=20=20= exc_set=20|=3D=20FE_INEXACT;=0A+=20=20else=20if=20(clear=20&=20= GFC_FPE_INEXACT)=0A+=20=20=20=20exc_clr=20|=3D=20FE_INEXACT;=0A+=0A+=20=20= fpsr_new=20=3D=20fpsr=20=3D=20__builtin_aarch64_get_fpsr();=0A+=20=20= fpsr_new=20&=3D=20~exc_clr;=0A+=20=20fpsr_new=20|=3D=20exc_set;=0A+=0A+=20= =20if=20(fpsr_new=20!=3D=20fpsr)=0A+=20=20=20=20= __builtin_aarch64_set_fpsr(fpsr_new);=0A+}=0A+=0A+=0A+void=0A= +get_fpu_state=20(void=20*state)=0A+{=0A+=20=20struct=20fenv=20*envp=20=3D= =20state;=0A+=20=20envp->__fpcr=20=3D=20__builtin_aarch64_get_fpcr();=0A= +=20=20envp->__fpsr=20=3D=20__builtin_aarch64_get_fpsr();=0A+}=0A+=0A+=0A= +void=0A+set_fpu_state=20(void=20*state)=0A+{=0A+=20=20struct=20fenv=20= *envp=20=3D=20state;=0A+=20=20__builtin_aarch64_set_fpcr(envp->__fpcr);=0A= +=20=20__builtin_aarch64_set_fpsr(envp->__fpsr);=0A+}=0A+=0A+=0A+int=0A= +get_fpu_rounding_mode=20(void)=0A+{=20=20=20=0A+=20=20unsigned=20int=20= fpcr=20=3D=20__builtin_aarch64_get_fpcr();=0A+=20=20fpcr=20&=3D=20= FPCR_RM_MASK;=0A+=0A+=20=20switch=20(fpcr)=0A+=20=20=20=20{=0A+=20=20=20=20= =20=20case=20FE_TONEAREST:=0A+=20=20=20=20=20=20=20=20return=20= GFC_FPE_TONEAREST;=0A+=20=20=20=20=20=20case=20FE_UPWARD:=0A+=20=20=20=20= =20=20=20=20return=20GFC_FPE_UPWARD;=0A+=20=20=20=20=20=20case=20= FE_DOWNWARD:=0A+=20=20=20=20=20=20=20=20return=20GFC_FPE_DOWNWARD;=0A+=20= =20=20=20=20=20case=20FE_TOWARDZERO:=0A+=20=20=20=20=20=20=20=20return=20= GFC_FPE_TOWARDZERO;=0A+=20=20=20=20=20=20default:=0A+=20=20=20=20=20=20=20= =20return=200;=20/*=20Should=20be=20unreachable.=20=20*/=0A+=20=20=20=20= }=0A+}=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=0A+=0A+=0A+void=0A= +set_fpu_rounding_mode=20(int=20round)=0A+{=0A+=20=20unsigned=20int=20= fpcr,=20round_mode;=0A+=0A+=20=20switch=20(round)=0A+=20=20=20=20{=0A+=20= =20=20=20case=20GFC_FPE_TONEAREST:=0A+=20=20=20=20=20=20round_mode=20=3D=20= FE_TONEAREST;=0A+=20=20=20=20=20=20break;=0A+=20=20=20=20case=20= GFC_FPE_UPWARD:=0A+=20=20=20=20=20=20round_mode=20=3D=20FE_UPWARD;=0A+=20= =20=20=20=20=20break;=0A+=20=20=20=20case=20GFC_FPE_DOWNWARD:=0A+=20=20=20= =20=20=20round_mode=20=3D=20FE_DOWNWARD;=0A+=20=20=20=20=20=20break;=0A+=20= =20=20=20case=20GFC_FPE_TOWARDZERO:=0A+=20=20=20=20=20=20round_mode=20=3D=20= FE_TOWARDZERO;=0A+=20=20=20=20=20=20break;=0A+=20=20=20=20default:=0A+=20= =20=20=20=20=20return;=20/*=20Should=20be=20unreachable.=20=20*/=0A+=20=20= =20=20}=0A+=0A+=20=20fpcr=20=3D=20__builtin_aarch64_get_fpcr();=0A+=0A+=20= =20/*=20Only=20set=20FPCR=20if=20requested=20mode=20is=20different=20= from=20current.=20=20*/=0A+=20=20round_mode=20=3D=20(fpcr=20^=20= round_mode)=20&=20FPCR_RM_MASK;=0A+=20=20if=20(round_mode=20!=3D=200)=0A= +=20=20=20=20__builtin_aarch64_set_fpcr(fpcr=20^=20round_mode);=0A+}=0A+=0A= +=0A+int=0A+support_fpu_rounding_mode=20(int=20mode=20= __attribute__((unused)))=0A+{=0A+=20=20return=201;=0A+}=0A+=0A+=0A+int=0A= +support_fpu_underflow_control=20(int=20kind=20__attribute__((unused)))=0A= +{=0A+=20=20/*=20Unsupported=20*/=0A+=20=20return=200;=0A+}=0A+=0A+=0A= +int=0A+get_fpu_underflow_mode=20(void)=0A+{=0A+=20=20/*=20Unsupported=20= */=0A+=20=20return=200;=0A+}=0A+=0A+=0A+void=0A+set_fpu_underflow_mode=20= (int=20gradual=20__attribute__((unused)))=0A+{=0A+=20=20/*=20Unsupported=20= */=0A+}=0A+=0Adiff=20--git=20a/libgfortran/configure.host=20= b/libgfortran/configure.host=0Aindex=20e9d92c9d34dd..3d6c2db7772e=20= 100644=0A---=20a/libgfortran/configure.host=0A+++=20= b/libgfortran/configure.host=0A@@=20-39,17=20+39,29=20@@=20if=20test=20= "x${have_feenableexcept}"=20=3D=20"xyes";=20then=0A=20=20=20= ieee_support=3D'yes'=0A=20fi=0A=20=0A-#=20x86=20asm=20should=20be=20used=20= instead=20of=20glibc,=20since=20glibc=20doesn't=20support=0A-#=20the=20= x86=20denormal=20exception.=0A=20case=20"${host_cpu}"=20in=0A+=0A+=20=20= #=20x86=20asm=20should=20be=20used=20instead=20of=20glibc,=20since=20= glibc=20doesn't=20support=0A+=20=20#=20the=20x86=20denormal=20exception.=0A= =20=20=20i?86=20|=20x86_64)=0A=20=20=20=20=20if=20test=20= "x${have_soft_float}"=20=3D=20"xyes";=20then=0A=20=20=20=20=20=20=20= fpu_host=3D'fpu-generic'=0A+=20=20=20=20=20=20ieee_support=3D'no'=0A=20=20= =20=20=20else=0A=20=20=20=20=20=20=20fpu_host=3D'fpu-387'=0A+=20=20=20=20= =20=20ieee_support=3D'yes'=0A=20=20=20=20=20fi=0A-=20=20=20=20= ieee_support=3D'yes'=0A=20=20=20=20=20;;=0A+=0A+=20=20#=20use=20asm=20on=20= aarch64-darwin=0A+=20=20aarch64)=0A+=20=20=20=20case=20"${host_os}"=20in=0A= +=20=20=20=20=20=20darwin*)=0A+=20=20=20=20=20=20=20=20= fpu_host=3D'fpu-aarch64'=0A+=20=20=20=20=20=20=20=20ieee_support=3D'yes'=0A= +=20=20=20=20=20=20=20=20;;=0A+=20=20=20=20esac=0A+=0A=20esac=0A=20=0A=20= #=20Some=20targets=20require=20additional=20compiler=20options=20for=20= NaN/Inf.=0A= --Apple-Mail=_60519DB6-00A5-4714-827F-4A8013DB149F--