From: Carl Love <cel@us.ibm.com>
To: will schmidt <will_schmidt@vnet.ibm.com>,
segher@gcc.gnu.org, dje.gcc@gmail.com, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 2a/5] rs6000, vec_rlnm builtin fix arguments
Date: Mon, 12 Oct 2020 13:15:39 -0700 [thread overview]
Message-ID: <944b04f19285bb72789d3bad3b3d5c2de7e3c43f.camel@us.ibm.com> (raw)
In-Reply-To: <e90a2975967e28c463de74bd2df680e85127f472.camel@vnet.ibm.com>
Will, Segher:
This patch fixes an error in how the vec_rlnm() builtin parameters are
handled. The current test for this builtin are compile only. The
issue was found in the path that adds the 128-bit operands to the
vec_rlnm() builtin. The new test for the 128-bit operands is a compile
and run test.
Re-tested the patch on Power 9 with no regression errors.
Carl
-----------------------------------------------------------------
gcc/ChangeLog
2020-10-08 Carl Love <cel@us.ibm.com>
* config/rs6000/altivec.h (vec_rlnm): Fix bug in argument generation.
---
gcc/config/rs6000/altivec.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 8a2dcda0144..f7720d136c9 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -183,7 +183,7 @@
#define vec_recipdiv __builtin_vec_recipdiv
#define vec_rlmi __builtin_vec_rlmi
#define vec_vrlnm __builtin_vec_rlnm
-#define vec_rlnm(a,b,c) (__builtin_vec_rlnm((a),((c)<<8)|(b)))
+#define vec_rlnm(a,b,c) (__builtin_vec_rlnm((a),((b)<<8)|(c)))
#define vec_rsqrt __builtin_vec_rsqrt
#define vec_rsqrte __builtin_vec_rsqrte
#define vec_signed __builtin_vec_vsigned
--
2.17.1
next prev parent reply other threads:[~2020-10-12 20:15 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-21 21:17 [Patch 0/5] rs6000, 128-bit Binary Integer Operations Carl Love
2020-09-21 23:56 ` [PATCH 1/5] RS6000 Add 128-bit Binary Integer sign extend operations Carl Love
2020-09-24 18:20 ` will schmidt
2020-10-05 18:51 ` Carl Love
2020-10-07 21:08 ` will schmidt
2020-10-12 20:15 ` Carl Love
2020-10-12 20:51 ` Segher Boessenkool
2020-10-12 20:43 ` Segher Boessenkool
2020-10-12 21:06 ` Carl Love
2020-09-21 23:56 ` [PATCH 2/5] RS6000 add 128-bit Integer Operations Carl Love
2020-09-24 18:21 ` will schmidt
2020-10-05 18:52 ` [PATCH 2a/5] rs6000, vec_rlnm builtin fix arguments Carl Love
2020-10-07 21:08 ` will schmidt
2020-10-12 20:15 ` Carl Love [this message]
2020-10-12 23:37 ` Segher Boessenkool
2020-10-05 18:52 ` [PATCH 2b/5] RS6000 add 128-bit Integer Operations Carl Love
2020-10-07 21:53 ` will schmidt
2020-10-12 20:16 ` Carl Love
2020-10-13 0:23 ` Segher Boessenkool
2021-01-19 22:33 ` [PATCH 0/6 ver3] " Carl Love
2021-01-19 22:33 ` [PATCH 1/6 ver 3] rs6000, Fix arguments in altivec_vrlwmi and altivec_rlwdi builtins Carl Love
2021-01-19 22:33 ` [PATCH 2/6 ver 3] RS6000 Add 128-bit Binary Integer sign extend operations Carl Love
2021-01-19 22:33 ` [PATCH 3/6 ver 3] RS6000 add 128-bit Integer Operations part 1 Carl Love
2021-01-19 22:33 ` [PATCH 4/6 ver 3] Add TI to TD (128-bit DFP) and TD to TI support Carl Love
2021-01-19 22:33 ` [PATCH 5/6 ver 3] rs6000, Add test 128-bit shifts for just the int128 type Carl Love
2021-01-19 22:33 ` [PATCH 6/6 ver 3] Conversions between 128-bit integer and floating point values Carl Love
2020-09-21 23:56 ` [PATCH 3/5] Add TI to TD (128-bit DFP) and TD to TI support Carl Love
2020-09-24 18:21 ` will schmidt
2020-10-05 18:52 ` Carl Love
2020-10-08 14:22 ` will schmidt
2020-10-12 20:15 ` Carl Love
2020-09-21 23:56 ` [PATCH 4/5] Test 128-bit shifts for just the int128 type Carl Love
2020-09-24 18:21 ` will schmidt
2020-10-05 18:52 ` Carl Love
2020-10-08 14:50 ` will schmidt
2020-10-12 20:15 ` Carl Love
2020-09-21 23:57 ` [PATCH 5/5] Conversions between 128-bit integer and floating point values Carl Love
2020-09-24 18:22 ` will schmidt
2020-10-05 18:52 ` Carl Love
2020-10-08 15:35 ` will schmidt
2020-10-12 20:16 ` Carl Love
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