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[86.138.94.184]) by smtp.gmail.com with ESMTPSA id r62sm3361970wmd.15.2016.03.04.05.26.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Mar 2016 05:26:05 -0800 (PST) From: Andrew Burgess To: gcc-patches@gcc.gnu.org Cc: noamca@mellanox.com, Claudiu.Zissulescu@synopsys.com, Andrew Burgess Subject: [PATCH 08/10] gcc/arc: Mask integer 'L' operands to 32-bit Date: Fri, 04 Mar 2016 13:26:00 -0000 Message-Id: <944bac598a3deaabffaa9a5b199216b2cb551037.1457097757.git.andrew.burgess@embecosm.com> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes X-SW-Source: 2016-03/txt/msg00349.txt.bz2 When formatting 'L' operands (least significant word) only print 32-bits, don't sign extend to 64-bits. This commit could really be applied directly to the current GCC trunk, however, the only test I have for this issue right now relies on the nps400 bitops support. gcc/ChangeLog: * config/arc/arc.c (arc_print_operand): Print integer 'L' operands as 32-bits. gcc/testsuite/ChangeLog: * gcc.target/arc/movh_cl-1.c: New file. --- gcc/ChangeLog.NPS400 | 6 ++++++ gcc/config/arc/arc.c | 10 ++++------ gcc/testsuite/ChangeLog.NPS400 | 4 ++++ gcc/testsuite/gcc.target/arc/movh_cl-1.c | 27 +++++++++++++++++++++++++++ 4 files changed, 41 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/movh_cl-1.c diff --git a/gcc/ChangeLog.NPS400 b/gcc/ChangeLog.NPS400 index 8229d67..146370c 100644 --- a/gcc/ChangeLog.NPS400 +++ b/gcc/ChangeLog.NPS400 @@ -1,3 +1,9 @@ +2016-01-19 Joern Rennecke + Andrew Burgess + + * config/arc/arc.c (arc_print_operand): Print integer 'L' operands + as 32-bits. + 2013-02-19 Joern Rennecke Andrew Burgess diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index a75f200..dc885d3 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -3176,18 +3176,16 @@ arc_print_operand (FILE *file, rtx x, int code) else if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) { - rtx first, second; + rtx first, second, word; split_double (x, &first, &second); if((WORDS_BIG_ENDIAN) == 0) - fprintf (file, "0x%08" PRIx64, - code == 'L' ? INTVAL (first) : INTVAL (second)); + word = (code == 'L' ? first : second); else - fprintf (file, "0x%08" PRIx64, - code == 'L' ? INTVAL (second) : INTVAL (first)); - + word = (code == 'L' ? second : first); + fprintf (file, "0x%08" PRIx32, ((uint32_t) INTVAL (word))); } else output_operand_lossage ("invalid operand to %%H/%%L code"); diff --git a/gcc/testsuite/ChangeLog.NPS400 b/gcc/testsuite/ChangeLog.NPS400 index 22dec32..d658bd9 100644 --- a/gcc/testsuite/ChangeLog.NPS400 +++ b/gcc/testsuite/ChangeLog.NPS400 @@ -1,3 +1,7 @@ +2016-01-19 Andrew Burgess + + * gcc.target/arc/movh_cl-1.c: New file. + 2013-02-19 Joern Rennecke Andrew Burgess diff --git a/gcc/testsuite/gcc.target/arc/movh_cl-1.c b/gcc/testsuite/gcc.target/arc/movh_cl-1.c new file mode 100644 index 0000000..8fbea7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/movh_cl-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target arc*-mellanox-* } } */ +/* { dg-options "-O2 -mbitops" } */ + +struct thing +{ + union + { + int raw; + struct + { + unsigned a : 1; + unsigned b : 1; + }; + }; +}; + +extern void func (int); + +void +blah () +{ + struct thing xx; + xx.a = xx.b = 1; + func (xx.raw); +} + +/* { dg-final { scan-assembler "movh\.cl r\[0-9\]+,0xc0000000>>16" } } */ -- 2.6.4