From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 72007 invoked by alias); 23 Jul 2018 10:39:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 71995 invoked by uid 89); 23 Jul 2018 10:39:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: =?ISO-8859-1?Q?No, score=-26.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=and, and=c2, H*r:sk:EUR02-H, Hx-languages-length:2551?= X-HELO: EUR02-HE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr10081.outbound.protection.outlook.com (HELO EUR02-HE1-obe.outbound.protection.outlook.com) (40.107.1.81) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 23 Jul 2018 10:39:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AbS67vfIZAh8hd9d5tICs1eNPwMBfmzM63WKwgdNZpY=; b=V5/eZzT9oz4yHQa53IE9Mc3FP0scPGT9F7NU1e1ZHoX4kuGWRzEDHvLi25BAvrm27MwVMc1cFwT68EeXR/1InCyOILszy8yi7xNXcb0F1nHklzTp0Wp9kPuIMAd7gvYLfiiUiX9K1eakuZKcg8zYgFjjJYnLLO84Kb+5HMRO/hk= Received: from [10.2.206.193] (217.140.96.140) by AM0PR08MB3427.eurprd08.prod.outlook.com (2603:10a6:208:dd::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.973.21; Mon, 23 Jul 2018 10:39:11 +0000 To: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft Cc: nd , Richard Earnshaw , James Greenhalgh From: Sam Tebbs Subject: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode Message-ID: <953dbdd2-e20c-4587-3e0d-ad1a65fc93c6@arm.com> Date: Mon, 23 Jul 2018 10:39:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------E07071625BC216454B929354" Return-Path: sam.tebbs@arm.com Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Sam.Tebbs@arm.com; Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-IsSubscribed: yes X-SW-Source: 2018-07/txt/msg01246.txt.bz2 This is a multi-part message in MIME format. --------------E07071625BC216454B929354 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-length: 1062 Hi all, This patch extends the aarch64_get_lane_zero_extendsi instruction definition to also cover DI mode. This prevents a redundant AND instruction from being generated due to the pattern failing to be matched. Example: typedef char v16qi __attribute__ ((vector_size (16))); unsigned long long foo (v16qi a) {   return a[0]; } Previously generated: foo:         umov    w0, v0.b[0]         and     x0, x0, 255         ret And now generates: foo:         umov    w0, v0.b[0]         ret Bootstrapped on aarch64-none-linux-gnu and tested on aarch64-none-elf with no regressions. gcc/ 2018-07-23  Sam Tebbs         * config/aarch64/aarch64-simd.md     (*aarch64_get_lane_zero_extendsi):         Rename to... (*aarch64_get_lane_zero_extend): ... This.         Use GPI iterator instead of SI mode. gcc/testsuite 2018-07-23  Sam Tebbs         * gcc.target/aarch64/extract_zero_extend.c: New file --------------E07071625BC216454B929354 Content-Type: text/x-patch; name="23-07-2018--11-27-30.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="23-07-2018--11-27-30.patch" Content-length: 1492 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 89e38e6..15fb661 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3032,15 +3032,16 @@ [(set_attr "type" "neon_to_gp")] ) -(define_insn "*aarch64_get_lane_zero_extendsi" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI +(define_insn "*aarch64_get_lane_zero_extend" + [(set (match_operand:GPI 0 "register_operand" "=r") + (zero_extend:GPI (vec_select: (match_operand:VDQQH 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] "TARGET_SIMD" { - operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); + operands[2] = aarch64_endian_lane_rtx (mode, + INTVAL (operands[2])); return "umov\\t%w0, %1.[%2]"; } [(set_attr "type" "neon_to_gp")] diff --git a/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c b/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c new file mode 100644 index 0000000..40d307a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +typedef char v16qi __attribute__ ((vector_size (16))); + +unsigned long long +foo (v16qi a) +{ + /* { dg-final { scan-assembler "umov\\t" } } */ + /* { dg-final { scan-assembler-not "and\\t" } } */ + return a[0]; +} + --------------E07071625BC216454B929354--