From: Peter Bergner <bergner@linux.ibm.com>
To: Jeff Law <jlaw@tachyum.com>, GCC Patches <gcc-patches@gcc.gnu.org>
Cc: Segher Boessenkool <segher@kernel.crashing.org>,
Michael Meissner <meissner@linux.ibm.com>
Subject: Re: Aligning stack offsets for spills
Date: Thu, 10 Jun 2021 14:28:34 -0500 [thread overview]
Message-ID: <960271b1-f8e5-48a1-576a-e655babd4e32@linux.ibm.com> (raw)
In-Reply-To: <98179c8e-bcec-83ed-5b99-6f54791bd7cd@tachyum.com>
On 6/7/21 2:00 PM, Jeff Law wrote:
> I can't divulge many of the details right now, but one of the quirks of our
> architecture is that reg+d addressing modes for our vector loads/stores require
> the displacement to be aligned. This is an artifact of how these instructions
> are encoded.
Given what you're describing, it sounds like POWER has something similar.
Our reg+displacement addressing uses 16-bit displacements using D, DS or DQ
operand fields. The D field encodes the entire 16-bits, but the DS and DQ
fields only encode 14-bits and 12-bits respectively. The DS and DQ operands
have the same maximum displacement as D operands, we just force that their
bottom 2-bits/4-bits must be zero, so we don't need to include them in the
insn encoding. I believe this is all just handled in our legitimate address
routines, but maybe Segher and/or Mike can correct me if I'm wrong?
Peter
next prev parent reply other threads:[~2021-06-10 19:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 19:00 Jeff Law
2021-06-08 6:56 ` Richard Biener
2021-06-08 15:00 ` Jeff Law
2021-06-08 14:08 ` Michael Matz
2021-06-08 14:47 ` Jeff Law
2021-06-08 14:55 ` Jakub Jelinek
2021-06-08 15:06 ` H.J. Lu
2021-06-08 15:18 ` Jeff Law
2021-06-08 15:56 ` Michael Matz
2021-06-10 22:49 ` Jeff Law
2021-06-10 19:28 ` Peter Bergner [this message]
2021-06-10 21:34 ` Segher Boessenkool
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