From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id BB6443858C78 for ; Thu, 16 Nov 2023 18:27:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BB6443858C78 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BB6443858C78 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::631 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700159274; cv=none; b=Ah3Gh3dUriWM8xV+95hd1CNqaR5UMUZfQvPgGRJGXR8nIu10yDRv3EZPQqV+LxQ7GTZVBmEsh//iyiF4i4LoZbB1A1W6PJQM2A6ws7q8UzCPpqnfFdA4KNSlXS+L8mV/cmeiVLUHcp2qEhk+B1gOZ9A34Ui6/AyvQTbA5CxChIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700159274; c=relaxed/simple; bh=z6dIHZGAa21OdItJmv2u3FmSZ5ifAOKBvWYwP6nJjxg=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:To:From; b=WAAEdFlaS//AWMXhcCAKkJDUCR2quyVKMAp3KKR/DGi3L06Ubrkfotyd658YfF/y8a4yEsiGkj/U7+s9jE1/N3RjP6TVgoXd5BYQWRgdAp5GoMCtgqbeXGV96ZBqWN4QiPEMJPMY1pS6iaqzJnOc2QAu/ka2blBRTdmpwZIFzC4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1cc5b705769so10202105ad.0 for ; Thu, 16 Nov 2023 10:27:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1700159271; x=1700764071; darn=gcc.gnu.org; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=ZFRHOdnSSg4duS1rd/02SARCLSY7b8L5EF9CC7V44GE=; b=giwBHn2yJdngurntyQ4X16dWyCf5I0qy4bPDDJfDyJ5ZIDAv9oL6d7XGjBzuC5dH0j 6Ls0gMx7HU8w0yKlXSU4W1z5kgmTnW533bVWoGYLa5IiuUe4OU0xpWe77cA6As21NGyi 5DB51wF+NvFjDWYHl2nQvUqnPImGtAMi+Kom6WQfVlE97PAnFpUcmBt9VASf7Q9D+sN3 iPQi3qTuzREAIhdtBVUff6O18oC7wNSnJl1paqFBZiVEDUjeACil/bC2/KUu06DlVF07 x/yv2MGrhX+DiFy6hOpRy+FXd1tOHPzAPEXKLwimD3SNex110f3JrBlnJ+JqkFJJQqcJ k/nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700159271; x=1700764071; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ZFRHOdnSSg4duS1rd/02SARCLSY7b8L5EF9CC7V44GE=; b=LyelydxFk+dUT5qOddkUvfFigds0JGDuq8DJ3FzfW3tprpAARfgLvFXIZs/LE8YoIe Qb8m9aPbnYHllua5nslekzihpV40kvK+pxyRU74GHQbA8/HOux5SW8Zt1GFrVL2/phM1 M/Q9nRs1z9vHBxfiiNBqvVKheSkP/psUmiZQN3tqdRIQfNpNsRVnS1miZ1XpCvlIhc40 z7QZqV9rZMSUxi9Y2VxbX0ykC1iT1IL8v5NAJEH9zENTSbywif467CLZ+DHldioCHrjm ZEX1F2goQuVsRNkx0rMvr42+zU74hmgrVOsOIy3G5nQlUvuQF1DwleSdAhnCtTU13HrC QNRw== X-Gm-Message-State: AOJu0YzyAtp39IGiN4fmuA3YCq8BG1X2K7A3EBQOtm98mZBK5JckT6WS PxBhXsjuT/Ook2MDmEsEpdf3en89VI2KBayVWu0= X-Google-Smtp-Source: AGHT+IHSDxHHQxdDU7a1Z/JT6lVIazUi9JAZMjiZAn+JPzw7PbCClEkZjCfRjbmNUvEw7emeS9ev9Q== X-Received: by 2002:a17:902:e88e:b0:1cc:5505:fff3 with SMTP id w14-20020a170902e88e00b001cc5505fff3mr12482913plg.30.1700159270701; Thu, 16 Nov 2023 10:27:50 -0800 (PST) Received: from [10.0.17.83] ([12.44.203.122]) by smtp.gmail.com with ESMTPSA id l18-20020a170903121200b001c5dea67c26sm9515795plh.233.2023.11.16.10.27.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Nov 2023 10:27:50 -0800 (PST) Message-ID: <965452de-5876-4d94-9943-69b55780c76d@rivosinc.com> Date: Thu, 16 Nov 2023 10:27:50 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Committed] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557] Content-Language: en-US To: Kito Cheng Cc: gcc-patches@gcc.gnu.org, gnu-toolchain@rivosinc.com References: <20231115233042.557245-1-ewlu@rivosinc.com> From: Edwin Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed! On 11/15/2023 11:34 PM, Kito Cheng wrote: > ohhh, thanks for fixing that, LGTM! > > On Thu, Nov 16, 2023 at 7:31 AM Edwin Lu wrote: >> Fix __riscv_unaligned_fast/slow/avoid macro name to >> __riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec >> >> gcc/ChangeLog: >> >> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro name >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/attribute-1.c: update macro name >> * gcc.target/riscv/attribute-4.c: ditto >> * gcc.target/riscv/attribute-5.c: ditto >> * gcc.target/riscv/predef-align-1.c: ditto >> * gcc.target/riscv/predef-align-2.c: ditto >> * gcc.target/riscv/predef-align-3.c: ditto >> * gcc.target/riscv/predef-align-4.c: ditto >> * gcc.target/riscv/predef-align-5.c: ditto >> * gcc.target/riscv/predef-align-6.c: ditto >> >> Signed-off-by: Edwin Lu >> --- >> gcc/config/riscv/riscv-c.cc | 6 +++--- >> gcc/testsuite/gcc.target/riscv/attribute-1.c | 10 +++++----- >> gcc/testsuite/gcc.target/riscv/attribute-4.c | 8 ++++---- >> gcc/testsuite/gcc.target/riscv/attribute-5.c | 10 +++++----- >> gcc/testsuite/gcc.target/riscv/predef-align-1.c | 10 +++++----- >> gcc/testsuite/gcc.target/riscv/predef-align-2.c | 8 ++++---- >> gcc/testsuite/gcc.target/riscv/predef-align-3.c | 10 +++++----- >> gcc/testsuite/gcc.target/riscv/predef-align-4.c | 10 +++++----- >> gcc/testsuite/gcc.target/riscv/predef-align-5.c | 8 ++++---- >> gcc/testsuite/gcc.target/riscv/predef-align-6.c | 10 +++++----- >> 10 files changed, 45 insertions(+), 45 deletions(-) >> >> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc >> index b7f9ba204f7..dd1bd0596fc 100644 >> --- a/gcc/config/riscv/riscv-c.cc >> +++ b/gcc/config/riscv/riscv-c.cc >> @@ -109,11 +109,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) >> } >> >> if (riscv_user_wants_strict_align) >> - builtin_define_with_int_value ("__riscv_unaligned_avoid", 1); >> + builtin_define_with_int_value ("__riscv_misaligned_avoid", 1); >> else if (riscv_slow_unaligned_access_p) >> - builtin_define_with_int_value ("__riscv_unaligned_slow", 1); >> + builtin_define_with_int_value ("__riscv_misaligned_slow", 1); >> else >> - builtin_define_with_int_value ("__riscv_unaligned_fast", 1); >> + builtin_define_with_int_value ("__riscv_misaligned_fast", 1); >> >> if (TARGET_MIN_VLEN != 0) >> builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN); >> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c b/gcc/testsuite/gcc.target/riscv/attribute-1.c >> index abfb0b498e0..a39efb3e6ff 100644 >> --- a/gcc/testsuite/gcc.target/riscv/attribute-1.c >> +++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c >> @@ -4,13 +4,13 @@ int foo() >> { >> >> /* In absence of -m[no-]strict-align, default mcpu is currently >> - set to rocket. rocket has slow_unaligned_access=true. */ >> -#if !defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_slow is not set" >> + set to rocket. rocket has slow_misaligned_access=true. */ >> +#if !defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_slow is not set" >> #endif >> >> -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) >> -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" >> +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set" >> #endif >> >> return 0; >> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c b/gcc/testsuite/gcc.target/riscv/attribute-4.c >> index 545f87cb899..a5a95042a31 100644 >> --- a/gcc/testsuite/gcc.target/riscv/attribute-4.c >> +++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c >> @@ -3,12 +3,12 @@ >> int foo() >> { >> >> -#if !defined(__riscv_unaligned_avoid) >> -#error "__riscv_unaligned_avoid is not set" >> +#if !defined(__riscv_misaligned_avoid) >> +#error "__riscv_misaligned_avoid is not set" >> #endif >> >> -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" >> +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set" >> #endif >> >> return 0; >> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c b/gcc/testsuite/gcc.target/riscv/attribute-5.c >> index 753043c31e9..ad1a1811fa3 100644 >> --- a/gcc/testsuite/gcc.target/riscv/attribute-5.c >> +++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c >> @@ -3,13 +3,13 @@ >> int foo() >> { >> >> -/* Default mcpu is rocket which has slow_unaligned_access=true. */ >> -#if !defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_slow is not set" >> +/* Default mcpu is rocket which has slow_misaligned_access=true. */ >> +#if !defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_slow is not set" >> #endif >> >> -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) >> -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" >> +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set" >> #endif >> >> return 0; >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-1.c b/gcc/testsuite/gcc.target/riscv/predef-align-1.c >> index 9dde37a721e..fb8c5f74035 100644 >> --- a/gcc/testsuite/gcc.target/riscv/predef-align-1.c >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-1.c >> @@ -3,13 +3,13 @@ >> >> int main() { >> >> -/* thead-c906 default is cpu tune param unaligned access fast */ >> -#if !defined(__riscv_unaligned_fast) >> -#error "__riscv_unaligned_fast is not set" >> +/* thead-c906 default is cpu tune param misaligned access fast */ >> +#if !defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_fast is not set" >> #endif >> >> -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set" >> +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is unexpectedly set" >> #endif >> >> return 0; >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-2.c b/gcc/testsuite/gcc.target/riscv/predef-align-2.c >> index 33d604f5aa0..50ab67e04f5 100644 >> --- a/gcc/testsuite/gcc.target/riscv/predef-align-2.c >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-2.c >> @@ -3,12 +3,12 @@ >> >> int main() { >> >> -#if !defined(__riscv_unaligned_avoid) >> -#error "__riscv_unaligned_avoid is not set" >> +#if !defined(__riscv_misaligned_avoid) >> +#error "__riscv_misaligned_avoid is not set" >> #endif >> >> -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" >> +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set" >> #endif >> >> return 0; >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-3.c b/gcc/testsuite/gcc.target/riscv/predef-align-3.c >> index daf5718a39f..5c586907cb0 100644 >> --- a/gcc/testsuite/gcc.target/riscv/predef-align-3.c >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-3.c >> @@ -3,13 +3,13 @@ >> >> int main() { >> >> -/* thead-c906 default is cpu tune param unaligned access fast */ >> -#if !defined(__riscv_unaligned_fast) >> -#error "__riscv_unaligned_fast is not set" >> +/* thead-c906 default is cpu tune param misaligned access fast */ >> +#if !defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_fast is not set" >> #endif >> >> -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set" >> +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is unexpectedly set" >> #endif >> >> return 0; >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-4.c b/gcc/testsuite/gcc.target/riscv/predef-align-4.c >> index d46a46f252d..6fbdc7f7d41 100644 >> --- a/gcc/testsuite/gcc.target/riscv/predef-align-4.c >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-4.c >> @@ -3,13 +3,13 @@ >> >> int main() { >> >> -/* rocket default is cpu tune param unaligned access slow */ >> -#if !defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_slow is not set" >> +/* rocket default is cpu tune param misaligned access slow */ >> +#if !defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_slow is not set" >> #endif >> >> -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) >> -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" >> +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set" >> #endif >> >> return 0; >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-5.c b/gcc/testsuite/gcc.target/riscv/predef-align-5.c >> index 3aa25f8e0e0..4a40081d86d 100644 >> --- a/gcc/testsuite/gcc.target/riscv/predef-align-5.c >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-5.c >> @@ -3,12 +3,12 @@ >> >> int main() { >> >> -#if !defined(__riscv_unaligned_avoid) >> -#error "__riscv_unaligned_avoid is not set" >> +#if !defined(__riscv_misaligned_avoid) >> +#error "__riscv_misaligned_avoid is not set" >> #endif >> >> -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" >> +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set" >> #endif >> >> return 0; >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-6.c b/gcc/testsuite/gcc.target/riscv/predef-align-6.c >> index cb64d7e7778..18eb72cfc60 100644 >> --- a/gcc/testsuite/gcc.target/riscv/predef-align-6.c >> +++ b/gcc/testsuite/gcc.target/riscv/predef-align-6.c >> @@ -3,13 +3,13 @@ >> >> int main() { >> >> -/* rocket default is cpu tune param unaligned access slow */ >> -#if !defined(__riscv_unaligned_slow) >> -#error "__riscv_unaligned_slow is not set" >> +/* rocket default is cpu tune param misaligned access slow */ >> +#if !defined(__riscv_misaligned_slow) >> +#error "__riscv_misaligned_slow is not set" >> #endif >> >> -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) >> -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" >> +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast) >> +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set" >> #endif >> >> return 0; >> -- >> 2.34.1 >>