>>  ;; V has 32-bit unsigned immediates.  This happens to be the same constraint asIt should be 5-bit unsigned immediates>> ;  the csr_operand, but it's not CSR related.
>> (define_predicate "v_uimm_operand"
>>   (match_operand 0 "csr_operand"))
To make name consistent, it should be "vector_xxxx", so I suggest it to be "vector_scalar_shift_operand".

Thanks.


juzhe.zhong@rivai.ai