From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id F04EA3857C47 for ; Fri, 12 Nov 2021 19:49:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F04EA3857C47 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1ACJlqI0016038; Fri, 12 Nov 2021 19:49:52 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3c9x7rrj1j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Nov 2021 19:49:52 +0000 Received: from m0098393.ppops.net (m0098393.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 1ACJnqmR020646; Fri, 12 Nov 2021 19:49:52 GMT Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com with ESMTP id 3c9x7rrj13-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Nov 2021 19:49:52 +0000 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 1ACJmIq6017758; Fri, 12 Nov 2021 19:49:50 GMT Received: from b01cxnp22033.gho.pok.ibm.com (b01cxnp22033.gho.pok.ibm.com [9.57.198.23]) by ppma05wdc.us.ibm.com with ESMTP id 3c9ab655vk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Nov 2021 19:49:50 +0000 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1ACJnnkv54067530 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 12 Nov 2021 19:49:49 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 63EF2112064; Fri, 12 Nov 2021 19:49:49 +0000 (GMT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E43F2112061; Fri, 12 Nov 2021 19:49:48 +0000 (GMT) Received: from [9.65.75.193] (unknown [9.65.75.193]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP; Fri, 12 Nov 2021 19:49:48 +0000 (GMT) Message-ID: <973e8b4a-8cc5-7050-023e-712536e17058@linux.ibm.com> Date: Fri, 12 Nov 2021 13:49:48 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.3.0 Subject: PING: [PATCH] rs6000: MMA test case emits wrong code when building a vector pair Content-Language: en-US To: Segher Boessenkool , David Edelsohn Cc: Bill Schmidt , GCC Patches , Rajalakshmi Srinivasaraghavan References: <24684412-042a-0842-3a5e-1e62c0ae3691@linux.ibm.com> From: Peter Bergner In-Reply-To: <24684412-042a-0842-3a5e-1e62c0ae3691@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: UnNknXfpqIGq5M9NCbZt3Z5kW6csFIlQ X-Proofpoint-ORIG-GUID: zlBoieLnMvf1ObNp1EWWKwcO05JV6t7c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-12_05,2021-11-12_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 impostorscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111120103 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Nov 2021 19:49:55 -0000 I'd like to ping the following patch. Peter On 10/27/21 8:37 PM, Peter Bergner via Gcc-patches wrote: > PR102976 shows a test case where we generate wrong code when building > a vector pair from 2 vector registers. The bug here is that with unlucky > register assignments, we can clobber one of the input operands before > we write both registers of the output operand. The solution is to use > early-clobbers in the assemble pair and accumulator patterns. > > This passed bootstrap and regtesting with no regressions and our > OpenBLAS team has confirmed it fixes the issues they reported. > Ok for mainline? > > Ok for GCC 11 too after a few days on trunk? > > Peter > > > gcc/ > PR target/102976 > * config/rs6000/mma.md (*vsx_assemble_pair): Add early-clobber for > output operand. > (*mma_assemble_acc): Likewise. > > gcc/testsuite/ > PR target/102976 > * gcc.target/powerpc/pr102976.c: New test. > > diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md > index 1990a2183f6..f0ea99963f7 100644 > --- a/gcc/config/rs6000/mma.md > +++ b/gcc/config/rs6000/mma.md > @@ -339,7 +339,7 @@ (define_expand "vsx_assemble_pair" > }) > > (define_insn_and_split "*vsx_assemble_pair" > - [(set (match_operand:OO 0 "vsx_register_operand" "=wa") > + [(set (match_operand:OO 0 "vsx_register_operand" "=&wa") > (unspec:OO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa") > (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa")] > UNSPEC_MMA_ASSEMBLE))] > @@ -405,7 +405,7 @@ (define_expand "mma_assemble_acc" > }) > > (define_insn_and_split "*mma_assemble_acc" > - [(set (match_operand:XO 0 "fpr_reg_operand" "=d") > + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") > (unspec:XO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa") > (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa") > (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa") > diff --git a/gcc/testsuite/gcc.target/powerpc/pr102976.c b/gcc/testsuite/gcc.target/powerpc/pr102976.c > new file mode 100644 > index 00000000000..a8de8f056f1 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr102976.c > @@ -0,0 +1,14 @@ > +/* { dg-require-effective-target power10_ok } */ > +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ > + > +#include > +void > +bug (__vector_pair *dst) > +{ > + register vector unsigned char vec0 asm ("vs44"); > + register vector unsigned char vec1 asm ("vs32"); > + __builtin_vsx_build_pair (dst, vec0, vec1); > +} > + > +/* { dg-final { scan-assembler-times {xxlor[^,]*,44,44} 1 } } */ > +/* { dg-final { scan-assembler-times {xxlor[^,]*,32,32} 1 } } */ >