From 74cf1fd298e4923c106deaba3192423d48049559 Mon Sep 17 00:00:00 2001 From: Xionghu Luo Date: Fri, 14 May 2021 01:21:06 -0500 Subject: [PATCH 2/2] rs6000: Fold xxsel to vsel since they have same semantics gcc/ChangeLog: * config/rs6000/altivec.md: Add vsx register constraints. * config/rs6000/vsx.md (vsx_xxsel): Delete. (vsx_xxsel2): Likewise. (vsx_xxsel3): Likewise. (vsx_xxsel4): Likewise. --- gcc/config/rs6000/altivec.md | 56 +++++++++++++++++++-------------- gcc/config/rs6000/vsx.md | 61 ------------------------------------ 2 files changed, 32 insertions(+), 85 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index df8f24701d0..6ce3eb9dbc8 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -668,59 +668,67 @@ (define_insn "*altivec_gev4sf" [(set_attr "type" "veccmp")]) (define_insn "altivec_vsel" - [(set (match_operand:VM 0 "altivec_register_operand" "=v") + [(set (match_operand:VM 0 "altivec_register_operand" "=wa,v") (ior:VM (and:VM - (not:VM (match_operand:VM 3 "altivec_register_operand" "v")) - (match_operand:VM 1 "altivec_register_operand" "v")) + (not:VM (match_operand:VM 3 "altivec_register_operand" "wa,v")) + (match_operand:VM 1 "altivec_register_operand" "wa,v")) (and:VM - (match_operand:VM 2 "altivec_register_operand" "v") - (match_operand:VM 4 "altivec_register_operand" "v"))))] + (match_operand:VM 2 "altivec_register_operand" "wa,v") + (match_operand:VM 4 "altivec_register_operand" "wa,v"))))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && rtx_equal_p (operands[2], operands[3])" - "vsel %0,%1,%4,%3" + "@ + xxsel %x0,%x1,%x4,%x3 + vsel %0,%1,%4,%3" [(set_attr "type" "vecmove")]) (define_insn "altivec_vsel2" - [(set (match_operand:VM 0 "altivec_register_operand" "=v") + [(set (match_operand:VM 0 "altivec_register_operand" "=wa,v") (ior:VM (and:VM - (not:VM (match_operand:VM 3 "altivec_register_operand" "v")) - (match_operand:VM 1 "altivec_register_operand" "v")) + (not:VM (match_operand:VM 3 "altivec_register_operand" "wa,v")) + (match_operand:VM 1 "altivec_register_operand" "wa,v")) (and:VM - (match_operand:VM 2 "altivec_register_operand" "v") - (match_operand:VM 4 "altivec_register_operand" "v"))))] + (match_operand:VM 2 "altivec_register_operand" "wa,v") + (match_operand:VM 4 "altivec_register_operand" "wa,v"))))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && rtx_equal_p (operands[4], operands[3])" - "vsel %0,%1,%2,%3" + "@ + xxsel %x0,%x1,%x2,%x3 + vsel %0,%1,%2,%3" [(set_attr "type" "vecmove")]) (define_insn "altivec_vsel3" - [(set (match_operand:VM 0 "altivec_register_operand" "=v") + [(set (match_operand:VM 0 "altivec_register_operand" "=wa,v") (ior:VM (and:VM - (match_operand:VM 1 "altivec_register_operand" "v") - (match_operand:VM 2 "altivec_register_operand" "v")) + (match_operand:VM 1 "altivec_register_operand" "wa,v") + (match_operand:VM 2 "altivec_register_operand" "wa,v")) (and:VM - (not:VM (match_operand:VM 3 "altivec_register_operand" "v")) - (match_operand:VM 4 "altivec_register_operand" "v"))))] + (not:VM (match_operand:VM 3 "altivec_register_operand" "wa,v")) + (match_operand:VM 4 "altivec_register_operand" "wa,v"))))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && rtx_equal_p (operands[1], operands[3])" - "vsel %0,%4,%2,%3" + "@ + xxsel %x0,%x4,%x2,%x3 + vsel %0,%4,%2,%3" [(set_attr "type" "vecmove")]) (define_insn "altivec_vsel4" - [(set (match_operand:VM 0 "altivec_register_operand" "=v") + [(set (match_operand:VM 0 "altivec_register_operand" "=wa,v") (ior:VM (and:VM - (match_operand:VM 1 "altivec_register_operand" "v") - (match_operand:VM 2 "altivec_register_operand" "v")) + (match_operand:VM 1 "altivec_register_operand" "wa,v") + (match_operand:VM 2 "altivec_register_operand" "wa,v")) (and:VM - (not:VM (match_operand:VM 3 "altivec_register_operand" "v")) - (match_operand:VM 4 "altivec_register_operand" "v"))))] + (not:VM (match_operand:VM 3 "altivec_register_operand" "wa,v")) + (match_operand:VM 4 "altivec_register_operand" "wa,v"))))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && rtx_equal_p (operands[2], operands[3])" - "vsel %0,%4,%1,%3" + "@ + xxsel %x0,%x4,%x1,%x3 + vsel %0,%4,%1,%3" [(set_attr "type" "vecmove")]) ;; Fused multiply add. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f53de7bf34c..55d830d0f20 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2104,67 +2104,6 @@ (define_insn "*vsx_ge__p" "xvcmpgep. %x0,%x1,%x2" [(set_attr "type" "")]) -;; Vector select -(define_insn "vsx_xxsel" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L - (and:VSX_L - (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" ",wa")) - (match_operand:VSX_L 1 "vsx_register_operand" ",wa")) - (and:VSX_L - (match_operand:VSX_L 2 "vsx_register_operand" ",wa") - (match_operand:VSX_L 4 "vsx_register_operand" ",wa"))))] - "VECTOR_MEM_VSX_P (mode) - && rtx_equal_p (operands[2], operands[3])" - "xxsel %x0,%x1,%x4,%x3" - [(set_attr "type" "vecmove") - (set_attr "isa" "")]) - -(define_insn "vsx_xxsel2" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L - (and:VSX_L - (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" ",wa")) - (match_operand:VSX_L 1 "vsx_register_operand" ",wa")) - (and:VSX_L - (match_operand:VSX_L 2 "vsx_register_operand" ",wa") - (match_operand:VSX_L 4 "vsx_register_operand" ",wa"))))] - "VECTOR_MEM_VSX_P (mode) - && rtx_equal_p (operands[4], operands[3])" - "xxsel %x0,%x1,%x2,%x3" - [(set_attr "type" "vecmove") - (set_attr "isa" "")]) - -(define_insn "vsx_xxsel3" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L - (and:VSX_L - (match_operand:VSX_L 1 "vsx_register_operand" ",wa") - (match_operand:VSX_L 2 "vsx_register_operand" ",wa")) - (and:VSX_L - (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" ",wa")) - (match_operand:VSX_L 4 "vsx_register_operand" ",wa"))))] - "VECTOR_MEM_VSX_P (mode) - && rtx_equal_p (operands[1], operands[3])" - "xxsel %x0,%x4,%x2,%x3" - [(set_attr "type" "vecmove") - (set_attr "isa" "")]) - -(define_insn "vsx_xxsel4" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L - (and:VSX_L - (match_operand:VSX_L 1 "vsx_register_operand" ",wa") - (match_operand:VSX_L 2 "vsx_register_operand" ",wa")) - (and:VSX_L - (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" ",wa")) - (match_operand:VSX_L 4 "vsx_register_operand" ",wa"))))] - "VECTOR_MEM_VSX_P (mode) - && rtx_equal_p (operands[2], operands[3])" - "xxsel %x0,%x4,%x1,%x3" - [(set_attr "type" "vecmove") - (set_attr "isa" "")]) - ;; Copy sign (define_insn "vsx_copysign3" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") -- 2.25.1