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From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: "Robin Dapp" <rdapp.gcc@gmail.com>,
	 yanzhang.wang <yanzhang.wang@intel.com>,
	 gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "Robin Dapp" <rdapp.gcc@gmail.com>,
	 Kito.cheng <kito.cheng@sifive.com>,  pan2.li <pan2.li@intel.com>
Subject: Re: Re: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg.
Date: Wed, 21 Jun 2023 14:33:09 +0800	[thread overview]
Message-ID: <97DAB2E16FC06C0D+202306211433091419866@rivai.ai> (raw)
In-Reply-To: <5f87af5c-3571-1fd1-b52a-ff723dd30361@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 620 bytes --]

Oh. Yes. Thanks for Robin pointing this.

@yanzhang, could you refine this patch more deeply to gain more optimizations ?

Thanks.


juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-06-21 14:27
To: yanzhang.wang; gcc-patches
CC: rdapp.gcc; juzhe.zhong; kito.cheng; pan2.li
Subject: Re: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg.
Hi Yanzhang,
 
while I appreciate the optimization, I'm a bit wary about just adding a special
case for "0".  Is that so common? Wouldn't we also like to have
  * pow2_p (val) == << val and others?
 
* 1 should also be covered.
 
Regards
Robin
 

  reply	other threads:[~2023-06-21  6:33 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-21  6:08 yanzhang.wang
2023-06-21  6:20 ` juzhe.zhong
2023-06-21  6:54   ` Wang, Yanzhang
2023-06-21  6:23 ` juzhe.zhong
2023-06-21  6:27 ` Robin Dapp
2023-06-21  6:33   ` juzhe.zhong [this message]
2023-06-21  7:08     ` Wang, Yanzhang
2023-06-21  7:25       ` juzhe.zhong
2023-07-28 11:50 ` [PATCH v2] " yanzhang.wang
2023-07-28 12:00   ` Kito Cheng
2023-07-28 12:00   ` Wang, Yanzhang
2023-07-28 12:31     ` Robin Dapp
2023-07-28 23:07       ` Jeff Law
2023-07-31 12:14         ` Wang, Yanzhang
2023-07-31 15:48           ` Jeff Law

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