* [PATCH 0/2] RISC-V: Add -m(no-)autovec-segment option
@ 2024-05-28 21:55 Patrick O'Neill
2024-05-28 21:55 ` [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment Patrick O'Neill
2024-05-28 21:55 ` [PATCH 2/2] RISC-V: Fix testcases renamed test flag options Patrick O'Neill
0 siblings, 2 replies; 6+ messages in thread
From: Patrick O'Neill @ 2024-05-28 21:55 UTC (permalink / raw)
To: gcc-patches; +Cc: gkm, jeffreyalaw, vineetg, ewlu, Patrick O'Neill
Rebased and combined these two patches into a series for precommit-CI to
properly test.
Edwin Lu (1):
RISC-V: Fix testcases renamed test flag options
Greg McGary (1):
RISC-V: add option -m(no-)autovec-segment
gcc/config/riscv/autovec.md | 4 +-
gcc/config/riscv/riscv-opts.h | 5 ++
gcc/config/riscv/riscv.opt | 4 ++
.../gcc.target/riscv/rvv/autovec/no-segment.c | 61 +++++++++++++++++++
.../autovec/struct/mask_struct_load_noseg-1.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-2.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-3.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-4.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-5.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-6.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-7.c | 6 ++
.../struct/mask_struct_load_noseg_run-1.c | 4 ++
.../struct/mask_struct_load_noseg_run-2.c | 4 ++
.../struct/mask_struct_load_noseg_run-3.c | 4 ++
.../struct/mask_struct_load_noseg_run-4.c | 4 ++
.../struct/mask_struct_load_noseg_run-5.c | 4 ++
.../struct/mask_struct_load_noseg_run-6.c | 4 ++
.../struct/mask_struct_load_noseg_run-7.c | 4 ++
.../struct/mask_struct_store_noseg-1.c | 6 ++
.../struct/mask_struct_store_noseg-2.c | 6 ++
.../struct/mask_struct_store_noseg-3.c | 6 ++
.../struct/mask_struct_store_noseg-4.c | 6 ++
.../struct/mask_struct_store_noseg-5.c | 6 ++
.../struct/mask_struct_store_noseg-6.c | 6 ++
.../struct/mask_struct_store_noseg-7.c | 6 ++
.../struct/mask_struct_store_noseg_run-1.c | 4 ++
.../struct/mask_struct_store_noseg_run-2.c | 4 ++
.../struct/mask_struct_store_noseg_run-3.c | 4 ++
.../struct/mask_struct_store_noseg_run-4.c | 4 ++
.../struct/mask_struct_store_noseg_run-5.c | 4 ++
.../struct/mask_struct_store_noseg_run-6.c | 4 ++
.../struct/mask_struct_store_noseg_run-7.c | 4 ++
.../rvv/autovec/struct/struct_vect_noseg-1.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-10.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-11.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-12.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-13.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-14.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-15.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-16.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-17.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-18.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-2.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-3.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-4.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-5.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-6.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-7.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-8.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-9.c | 7 +++
.../autovec/struct/struct_vect_noseg_run-1.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-10.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-11.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-12.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-13.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-14.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-15.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-16.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-17.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-18.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-2.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-3.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-4.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-5.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-6.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-7.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-8.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-9.c | 4 ++
gcc/tree-vect-stmts.cc | 3 +-
69 files changed, 411 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
--
2.43.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment
2024-05-28 21:55 [PATCH 0/2] RISC-V: Add -m(no-)autovec-segment option Patrick O'Neill
@ 2024-05-28 21:55 ` Patrick O'Neill
2024-05-28 22:03 ` Vineet Gupta
2024-05-29 13:19 ` Robin Dapp
2024-05-28 21:55 ` [PATCH 2/2] RISC-V: Fix testcases renamed test flag options Patrick O'Neill
1 sibling, 2 replies; 6+ messages in thread
From: Patrick O'Neill @ 2024-05-28 21:55 UTC (permalink / raw)
To: gcc-patches; +Cc: gkm, jeffreyalaw, vineetg, ewlu
From: Greg McGary <gkm@rivosinc.com>
Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This is useful for
performance experiments.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_mask_len_load_lanes, vec_mask_len_store_lanes):
Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT
* gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New macro.
* gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option.
* gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero.
* testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c,
testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests.
---
gcc/config/riscv/autovec.md | 4 +-
gcc/config/riscv/riscv-opts.h | 5 ++
gcc/config/riscv/riscv.opt | 4 ++
.../gcc.target/riscv/rvv/autovec/no-segment.c | 61 +++++++++++++++++++
.../autovec/struct/mask_struct_load_noseg-1.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-2.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-3.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-4.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-5.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-6.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-7.c | 6 ++
.../struct/mask_struct_load_noseg_run-1.c | 4 ++
.../struct/mask_struct_load_noseg_run-2.c | 4 ++
.../struct/mask_struct_load_noseg_run-3.c | 4 ++
.../struct/mask_struct_load_noseg_run-4.c | 4 ++
.../struct/mask_struct_load_noseg_run-5.c | 4 ++
.../struct/mask_struct_load_noseg_run-6.c | 4 ++
.../struct/mask_struct_load_noseg_run-7.c | 4 ++
.../struct/mask_struct_store_noseg-1.c | 6 ++
.../struct/mask_struct_store_noseg-2.c | 6 ++
.../struct/mask_struct_store_noseg-3.c | 6 ++
.../struct/mask_struct_store_noseg-4.c | 6 ++
.../struct/mask_struct_store_noseg-5.c | 6 ++
.../struct/mask_struct_store_noseg-6.c | 6 ++
.../struct/mask_struct_store_noseg-7.c | 6 ++
.../struct/mask_struct_store_noseg_run-1.c | 4 ++
.../struct/mask_struct_store_noseg_run-2.c | 4 ++
.../struct/mask_struct_store_noseg_run-3.c | 4 ++
.../struct/mask_struct_store_noseg_run-4.c | 4 ++
.../struct/mask_struct_store_noseg_run-5.c | 4 ++
.../struct/mask_struct_store_noseg_run-6.c | 4 ++
.../struct/mask_struct_store_noseg_run-7.c | 4 ++
.../rvv/autovec/struct/struct_vect_noseg-1.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-10.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-11.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-12.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-13.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-14.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-15.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-16.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-17.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-18.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-2.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-3.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-4.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-5.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-6.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-7.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-8.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-9.c | 7 +++
.../autovec/struct/struct_vect_noseg_run-1.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-10.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-11.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-12.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-13.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-14.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-15.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-16.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-17.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-18.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-2.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-3.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-4.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-5.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-6.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-7.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-8.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-9.c | 4 ++
gcc/tree-vect-stmts.cc | 3 +-
69 files changed, 411 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 87d4171bc89..2a7131de749 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -282,7 +282,7 @@
(match_operand:<VM> 2 "vector_mask_operand")
(match_operand 3 "autovec_length_operand")
(match_operand 4 "const_0_operand")]
- "TARGET_VECTOR"
+ "TARGET_VECTOR_AUTOVEC_SEGMENT"
{
riscv_vector::expand_lanes_load_store (operands, true);
DONE;
@@ -295,7 +295,7 @@
(match_operand:<VM> 2 "vector_mask_operand")
(match_operand 3 "autovec_length_operand")
(match_operand 4 "const_0_operand")]
- "TARGET_VECTOR"
+ "TARGET_VECTOR_AUTOVEC_SEGMENT"
{
riscv_vector::expand_lanes_load_store (operands, false);
DONE;
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1b2dd5757a8..bcd8731a1a9 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -160,4 +160,9 @@ enum riscv_tls_type {
TLS_DESCRIPTORS
};
+/* On some microarchitectures, vector segment loads and stores are excessively
+ expensive, so predicate the generation of those instrunctions. */
+#define TARGET_VECTOR_AUTOVEC_SEGMENT \
+ (TARGET_VECTOR && riscv_mautovec_segment)
+
#endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 87f58332016..b92cd458b74 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -628,3 +628,7 @@ Specify TLS dialect.
mfence-tso
Target Var(TARGET_FENCE_TSO) Init(1)
Specifies whether the fence.tso instruction should be used.
+
+mautovec-segment
+Target Integer Var(riscv_mautovec_segment) Init(1)
+Enable (default) or disable generation of vector segment load/store instructions.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
new file mode 100644
index 00000000000..b0feccf853f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -mno-autovec-segment" } */
+
+enum e { c, d };
+enum g { f };
+
+struct h
+{
+ float x, w;
+};
+
+struct k
+{
+ short z, y, i, j;
+};
+
+long r;
+struct h m, p;
+struct k *q;
+
+short
+l (float s)
+{
+ if (s <= 0.0f)
+ return 0;
+
+ if (s >= 5)
+ return 5;
+
+ return s;
+}
+
+struct n
+{
+ enum g colorspace;
+};
+
+struct n o (struct k *s, struct h *t)
+{
+ t->w = s->z;
+}
+
+void
+ClutImageChannel (struct n *s, enum e t)
+{
+
+ while (s)
+ for (; r; r++)
+ {
+ o (q, &p);
+
+ if (t & d)
+ q->y = (&m + q->y)->x;
+
+ if (t)
+ q->z = l ((&m + q->z)->w);
+
+ if (s->colorspace)
+ q++;
+ }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
new file mode 100644
index 00000000000..277761263f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
new file mode 100644
index 00000000000..addeba0033d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
new file mode 100644
index 00000000000..c02cff002f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
new file mode 100644
index 00000000000..7b4be34bcf5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
new file mode 100644
index 00000000000..0f999187dd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
new file mode 100644
index 00000000000..5dc550b9206
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
new file mode 100644
index 00000000000..761b47e61e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
new file mode 100644
index 00000000000..072359548eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
new file mode 100644
index 00000000000..7118ea38927
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
new file mode 100644
index 00000000000..38608f56475
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
new file mode 100644
index 00000000000..5e565fd2e44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
new file mode 100644
index 00000000000..8bcaa2e340a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
new file mode 100644
index 00000000000..8328962fcbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
new file mode 100644
index 00000000000..db2a5cf908c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
new file mode 100644
index 00000000000..c7415ec86f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
new file mode 100644
index 00000000000..f0abda66ef0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
new file mode 100644
index 00000000000..4331c7bac13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
new file mode 100644
index 00000000000..599fbd78e02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
new file mode 100644
index 00000000000..1757b0e27b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
new file mode 100644
index 00000000000..0dea4f3300e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
new file mode 100644
index 00000000000..90b8432fbc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
new file mode 100644
index 00000000000..fcd9b0302a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
new file mode 100644
index 00000000000..5541a3a7105
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
new file mode 100644
index 00000000000..415d7cfd025
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
new file mode 100644
index 00000000000..e5471c2242f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
new file mode 100644
index 00000000000..178057f7724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
new file mode 100644
index 00000000000..91e24d64aa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
new file mode 100644
index 00000000000..5ce8bb7bae2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
new file mode 100644
index 00000000000..8d040bd2535
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*16,\s*e8,\s*m1,\s*t[au],\s*m[au]} 8 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
new file mode 100644
index 00000000000..9f533f4ff49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-10.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
new file mode 100644
index 00000000000..2b12ed16822
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-11.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
new file mode 100644
index 00000000000..265e2905653
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-12.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
new file mode 100644
index 00000000000..ff134ecbbc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-13.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
new file mode 100644
index 00000000000..06648125073
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-14.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
new file mode 100644
index 00000000000..356054bf6a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-15.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
new file mode 100644
index 00000000000..21d36c002d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-16.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
new file mode 100644
index 00000000000..7f9763682a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-17.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
new file mode 100644
index 00000000000..86bdc2ca8d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-18.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
new file mode 100644
index 00000000000..24fc8c745ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e16,\s*m1,\s*t[au],\s*m[au]} 8 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
new file mode 100644
index 00000000000..16f4fd366e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 17 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
new file mode 100644
index 00000000000..1d18033e174
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]} 46 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
new file mode 100644
index 00000000000..d5983ef95ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 17 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
new file mode 100644
index 00000000000..9b158b9b740
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
new file mode 100644
index 00000000000..d9495e77d7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
new file mode 100644
index 00000000000..5e239e8b934
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-8.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
new file mode 100644
index 00000000000..5248f2a39c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-9.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
new file mode 100644
index 00000000000..0e24c5772b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
new file mode 100644
index 00000000000..e095b769906
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
new file mode 100644
index 00000000000..549dd15ad22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
new file mode 100644
index 00000000000..8fa80cf6530
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
new file mode 100644
index 00000000000..9b0e3b7881d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
new file mode 100644
index 00000000000..34b871e7073
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-14.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
new file mode 100644
index 00000000000..4166903f11a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-15.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
new file mode 100644
index 00000000000..f86a3a7c6de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-16.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
new file mode 100644
index 00000000000..113c8c8fd72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-17.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
new file mode 100644
index 00000000000..a1436fab644
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-18.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
new file mode 100644
index 00000000000..2108b5e9592
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
new file mode 100644
index 00000000000..5640a7e66a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
new file mode 100644
index 00000000000..2bfda096552
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
new file mode 100644
index 00000000000..6c03a7caf3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
new file mode 100644
index 00000000000..4d216ae197c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
new file mode 100644
index 00000000000..d1a00f1aed6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
new file mode 100644
index 00000000000..a0a35a90e3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
new file mode 100644
index 00000000000..286a7efe2fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-9.c"
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 4219ad832db..34f5736ba00 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -11558,7 +11558,8 @@ vectorizable_load (vec_info *vinfo,
- (vec_num * j + i) * nunits);
/* remain should now be > 0 and < nunits. */
unsigned num;
- if (constant_multiple_p (nunits, remain, &num))
+ if (known_gt (remain, 0)
+ && constant_multiple_p (nunits, remain, &num))
{
tree ptype;
new_vtype
--
2.43.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] RISC-V: Fix testcases renamed test flag options
2024-05-28 21:55 [PATCH 0/2] RISC-V: Add -m(no-)autovec-segment option Patrick O'Neill
2024-05-28 21:55 ` [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment Patrick O'Neill
@ 2024-05-28 21:55 ` Patrick O'Neill
2024-05-28 22:05 ` Vineet Gupta
1 sibling, 1 reply; 6+ messages in thread
From: Patrick O'Neill @ 2024-05-28 21:55 UTC (permalink / raw)
To: gcc-patches; +Cc: gkm, jeffreyalaw, vineetg, ewlu
From: Edwin Lu <ewlu@rivosinc.com>
Some testcases still had --param=riscv-autovec-preference=_,
update to use -mrvv-vector-bits=_.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/no-segment.c: Update dejagnu flags
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c:
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c:
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c:
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c:
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c:
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c:
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c:
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c:
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c:
Ditto
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c | 2 +-
.../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c | 4 ++--
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c | 2 +-
.../riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c | 2 +-
33 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
index b0feccf853f..79d03612a22 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -mno-autovec-segment" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment" } */
enum e { c, d };
enum g { f };
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
index 072359548eb..dc577af816b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_load_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
index 7118ea38927..0bb4e599816 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_load_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
index 38608f56475..3d70c0dbca6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_load_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
index 5e565fd2e44..ca98fd52cbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_load_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
index 8bcaa2e340a..190b95a6669 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_load_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
index 8328962fcbe..769d709ce50 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_load_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
index db2a5cf908c..bcd31f3229c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_load_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
index fcd9b0302a0..ec7b3811982 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_store_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
index 5541a3a7105..ca3b3d77136 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_store_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
index 415d7cfd025..e4fdea08dd2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_store_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
index e5471c2242f..7f63d204349 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_store_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
index 178057f7724..df0448dcab9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_store_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
index 91e24d64aa3..e6268b36098 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_store_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
index 5ce8bb7bae2..0fdcb8ba85e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "mask_struct_store_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
index 0e24c5772b8..2a50b7133be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
#include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
index e095b769906..887a7f9a6e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
index 549dd15ad22..f99db9b8f6c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
index 8fa80cf6530..3c320991a0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
index 9b0e3b7881d..588c728968a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
index 34b871e7073..7d4d1bfc899 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-14.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
index 4166903f11a..c462a1cb925 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-15.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
index f86a3a7c6de..35d0febb029 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-16.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
index 113c8c8fd72..4cedba48683 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-17.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
index a1436fab644..2bf1cd6984d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-18.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
index 2108b5e9592..36772aaf900 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
#include "struct_vect_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
index 5640a7e66a9..58201220915 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
#include "struct_vect_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
index 2bfda096552..4ac2c39c4ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
#include "struct_vect_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
index 6c03a7caf3d..dd90a1771a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
#include "struct_vect_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
index 4d216ae197c..0efbee0db9c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
index d1a00f1aed6..c08d13063f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
index a0a35a90e3e..404f5d664f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
index 286a7efe2fb..e14ceb9cbf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
#include "struct_vect_run-9.c"
--
2.43.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment
2024-05-28 21:55 ` [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment Patrick O'Neill
@ 2024-05-28 22:03 ` Vineet Gupta
2024-05-29 13:19 ` Robin Dapp
1 sibling, 0 replies; 6+ messages in thread
From: Vineet Gupta @ 2024-05-28 22:03 UTC (permalink / raw)
To: Patrick O'Neill, gcc-patches; +Cc: gkm, jeffreyalaw, ewlu
On 5/28/24 14:55, Patrick O'Neill wrote:
> From: Greg McGary <gkm@rivosinc.com>
>
> Add option -m(no-)autovec-segment to enable/disable autovectorizer
> from emitting vector segment load/store instructions. This is useful for
> performance experiments.
>
> gcc/ChangeLog:
> * config/riscv/autovec.md (vec_mask_len_load_lanes, vec_mask_len_store_lanes):
> Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT
> * gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New macro.
> * gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option.
> * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero.
I think this middle-end change needs to be broken out, even if
eventually merged when committing, with its own test case.
-Vineet
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] RISC-V: Fix testcases renamed test flag options
2024-05-28 21:55 ` [PATCH 2/2] RISC-V: Fix testcases renamed test flag options Patrick O'Neill
@ 2024-05-28 22:05 ` Vineet Gupta
0 siblings, 0 replies; 6+ messages in thread
From: Vineet Gupta @ 2024-05-28 22:05 UTC (permalink / raw)
To: Patrick O'Neill, gcc-patches; +Cc: gkm, jeffreyalaw, ewlu
On 5/28/24 14:55, Patrick O'Neill wrote:
> From: Edwin Lu <ewlu@rivosinc.com>
>
> Some testcases still had --param=riscv-autovec-preference=_,
> update to use -mrvv-vector-bits=_.
And this can be squashed with prev one, maybe added Tested-by Edwin.
Thx,
-Vineet
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment
2024-05-28 21:55 ` [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment Patrick O'Neill
2024-05-28 22:03 ` Vineet Gupta
@ 2024-05-29 13:19 ` Robin Dapp
1 sibling, 0 replies; 6+ messages in thread
From: Robin Dapp @ 2024-05-29 13:19 UTC (permalink / raw)
To: Patrick O'Neill, gcc-patches
Cc: rdapp.gcc, gkm, jeffreyalaw, vineetg, ewlu
On 5/28/24 23:55, Patrick O'Neill wrote:
> From: Greg McGary <gkm@rivosinc.com>
>
> Add option -m(no-)autovec-segment to enable/disable autovectorizer
> from emitting vector segment load/store instructions. This is useful for
> performance experiments.
I think the question was raised before but does a vector tune model
with high segment permute costs help for that already? We didn't have
those when the patch was initially posted.
If so, we wouldn't need a specific option.
Regards
Robin
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-05-29 13:19 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-28 21:55 [PATCH 0/2] RISC-V: Add -m(no-)autovec-segment option Patrick O'Neill
2024-05-28 21:55 ` [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment Patrick O'Neill
2024-05-28 22:03 ` Vineet Gupta
2024-05-29 13:19 ` Robin Dapp
2024-05-28 21:55 ` [PATCH 2/2] RISC-V: Fix testcases renamed test flag options Patrick O'Neill
2024-05-28 22:05 ` Vineet Gupta
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